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Xinwei Guo

from Folsom, CA
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Also known as:
Xinwei G Shanghai, I Guo
Connected to:
Al J Guo, 81Alan W Guo, 33Alaw Guo, 51Albert F Guo, 33Andi Guo, 36Anna Guo, 30Baogang Guo, 64Binmiao Guo, 53Bolei Guo, 45Chunhua Guo, 63

Xinwei Guo Phones & Addresses

  • Folsom, CA
  • Minneapolis, MN
  • Sacramento, CA

Resumes

Resumes

Xinwei Guo Photo 1

Principal Engineer

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Location:
Bloomington, IN
Industry:
Semiconductors
Work:
Ruizheng Investment Company Jun 2013 - Aug 2013
Business Analyst
Micron Inc Jun 2013 - Aug 2013
Principal Engineer
Intel Corporation Jul 2001 - Dec 2009
Senior Staff Design Engineer
Education:
Indiana University Bloomington 2013 - 2017
Bachelors, Finance La Lumiere School 2010 - 2013
Fudan University 1994 - 2001
Huzhou High School
Skills:
Ic
Asic
Semiconductors
Cmos
Soc
Mixed Signal
Eda
Analog Circuit Design
Verilog
Software Development
Product Development
Embedded Systems
Engineering Management
Analog
Debugging
Simulations
Interests:
Photography
Reading Books
Exploring New Things
Basketball
Languages:
Mandarin
English
Xinwei Guo Photo 2

Xinwei Guo

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Xinwei Guo Photo 3

Xinwei Guo

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Publications

Us Patents

Non-Volatile Memory Including Reference Signal Path

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US Patent:
20140063897, Mar 6, 2014
Filed:
Aug 28, 2012
Appl. No.:
13/596934
Inventors:
Xinwei Guo - Folsom CA, US
Richard E. Fackenthal - Carmichael CA, US
International Classification:
G11C 11/21
US Classification:
365148
Abstract:
Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element.

Differential Amplifier Schemes For Sensing Memory Cells

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US Patent:
20220189514, Jun 16, 2022
Filed:
Dec 21, 2021
Appl. No.:
17/557825
Inventors:
- Boise ID, US
Xinwei Guo - Folsom CA, US
International Classification:
G11C 7/06
H03F 3/45
G11C 11/16
G11C 11/15
Abstract:
Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory tell based at least in part on the sense signal.

Differential Amplifier Sensing Schemes For Non-Switching State Compensation In A Memory Device

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US Patent:
20210335408, Oct 28, 2021
Filed:
Apr 21, 2021
Appl. No.:
17/236741
Inventors:
- Boise ID, US
Xinwei Guo - Folsom CA, US
International Classification:
G11C 11/22
G11C 11/4094
G11C 11/4091
Abstract:
Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.

Differential Amplifier Schemes For Sensing Memory Cells

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US Patent:
20210166736, Jun 3, 2021
Filed:
Dec 3, 2019
Appl. No.:
16/702422
Inventors:
- Boise ID, US
Xinwei Guo - Folsom CA, US
International Classification:
G11C 7/06
G11C 11/15
G11C 11/16
H03F 3/45
Abstract:
Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

Ferroelectric Memory Cell With Access Line Disturbance Mitigation

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US Patent:
20210020222, Jan 21, 2021
Filed:
Jul 17, 2019
Appl. No.:
16/514481
Inventors:
- Boise ID, US
Xinwei Guo - Folsom CA, US
International Classification:
G11C 11/22
Abstract:
Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.

Differential Amplifier Schemes For Sensing Memory Cells

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US Patent:
20200294573, Sep 17, 2020
Filed:
Apr 21, 2020
Appl. No.:
16/854239
Inventors:
- Boise ID, US
Stefan Frederik Schippers - Peschiera del Garda (VR), IT
Xinwei Guo - Folsom CA, US
International Classification:
G11C 11/4091
G11C 11/408
H03F 3/45
G11C 11/22
Abstract:
Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

Self-Referencing Sensing Schemes With Coupling Capacitance

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US Patent:
20200279590, Sep 3, 2020
Filed:
May 18, 2020
Appl. No.:
16/877133
Inventors:
- Boise ID, US
William A. Melton - Shingle Springs CA, US
Daniele Vimercati - El Dorado Hills CA, US
Xinwei Guo - Folsom CA, US
Yasuko Hattori - Folsom CA, US
International Classification:
G11C 7/06
G11C 7/08
G11C 11/4091
G11C 11/22
Abstract:
Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

Redundancy Array Column Decoder For Memory

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US Patent:
20200090726, Mar 19, 2020
Filed:
Sep 25, 2019
Appl. No.:
16/583033
Inventors:
- Boise ID, US
Xinwei Guo - Folsom CA, US
International Classification:
G11C 11/22
G11C 29/00
Abstract:
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.
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Xinwei Guo from Folsom, CA Get Report