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Xiaotian Zhang

from Palo Alto, CA
Age ~48
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Also known as:
Xiaohe A Liu, Xiao Tian Zhang, Xiao He Liu, Xiaotian Vhang, Xiaotian Zhanz, Liu Xiaohe
Phone and address:
445 Wilton Ave, Palo Alto, CA 94306
Related to:
Guiling ZhangTing D Liu, 53Toai Chin, 53Hong Yu, 63Ailing Zhang, 85
Connected to:
Aaron N Zhang, 60Adelaide X Zhang, 48Aiai Zhang, 38Aijun Zhang, 70Airong Zhang, 71Alfred Zhang, 30Anderson Zhang, 34Angeline Zhang, 36Anli Zhang, 68Anming Zhang, 64

Xiaotian Zhang Phones & Addresses

  • 445 Wilton Ave, Palo Alto, CA 94306
  • Emeryville, CA
  • Moraga, CA
  • 132 7Th St, Philadelphia, PA 19106 (215) 923-0642
  • Haddon Township, NJ

Resumes

Resumes

Xiaotian Zhang Photo 1

Postdoctoral Researcher

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Location:
University Park, PA
Industry:
Semiconductors
Work:
Lawrence Berkeley National Laboratory
Postdoctoral Researcher
China Sunergy Corporation Nanjing China 2012 - Aug 2012
Internship
Education:
Penn State University 2014
Doctorates, Doctor of Philosophy, Philosophy Penn State University 2010 - 2014
Bachelors, Materials Science, Engineering
Skills:
Fesem
Raman Microscopy
Uv Vis Nir
Esem
Mathematica
Languages:
English
Mandarin
Xiaotian Zhang Photo 2

Xiaotian Zhang

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Xiaotian Zhang Photo 3

Xiaotian Zhang

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Xiaotian Zhang Photo 4

Xiaotian Zhang

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Publications

Us Patents

Semiconductor Package Having Improved Thermal Performance

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US Patent:
7612439, Nov 3, 2009
Filed:
Dec 22, 2005
Appl. No.:
11/316614
Inventors:
Xiaotian Zhang - San Jose CA, US
Argo Chang - Taipei, TW
James Lee - Taipei, TW
Ryan Huang - Taipei, TW
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US
Assignee:
Alpha and Omega Semiconductor Limited - Hamilton
International Classification:
H01L 23/495
H01L 23/48
US Classification:
257676, 257E23037, 257E23044, 257E23069, 257E23071, 257E23178, 257666, 257686, 257685, 257724, 257723, 257691, 257698, 257696, 257773, 257341
Abstract:
A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

High Current Semiconductor Power Device Soic Package

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US Patent:
7759775, Jul 20, 2010
Filed:
Oct 6, 2006
Appl. No.:
11/544453
Inventors:
Ming Sun - Sunnyvale CA, US
Xiaotian Zhang - San Jose CA, US
Lei Shi - Shanghai, CN
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 23/495
H01L 23/52
H01L 23/48
US Classification:
257666, 257E23031, 257E23033, 257E23037, 257E23052, 257E23044, 257E2301, 257E23024, 257E23026, 257672, 257676, 257675, 257692
Abstract:
A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Dfn Semiconductor Package Having Reduced Electrical Resistance

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US Patent:
7781265, Aug 24, 2010
Filed:
Mar 30, 2009
Appl. No.:
12/384100
Inventors:
Xiaotian Zhang - San Jose CA, US
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 21/44
H01L 21/48
H01L 21/50
US Classification:
438123, 438124, 257E21511
Abstract:
A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.

Compact Power Semiconductor Package And Method With Stacked Inductor And Integrated Circuit Die

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US Patent:
7868431, Jan 11, 2011
Filed:
Feb 23, 2009
Appl. No.:
12/391251
Inventors:
Tao Feng - Santa Clara CA, US
Xiaotian Zhang - San Jose CA, US
François Hébert - San Mateo CA, US
Ming Sun - Sunnyvale CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 23/495
H01L 21/44
H01L 21/48
H01L 21/50
H01F 5/00
US Classification:
257673, 438123, 336200, 257E2151, 257E23054
Abstract:
A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

Semiconductor Power Device Package Having A Lead Frame-Based Integrated Inductor

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US Patent:
7884452, Feb 8, 2011
Filed:
Nov 23, 2007
Appl. No.:
11/986673
Inventors:
Tao Feng - Santa Clara CA, US
Xiaotian Zhang - San Jose CA, US
François Hébert - San Mateo CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 23/495
H01F 5/00
US Classification:
257666, 336200, 257E21022, 257E2151
Abstract:
A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.

Use Of Discrete Conductive Layer In Semiconductor Device To Re-Route Bonding Wires For Semiconductor Device Package

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US Patent:
7884454, Feb 8, 2011
Filed:
Sep 11, 2008
Appl. No.:
12/209106
Inventors:
Jun Lu - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
Xiaobin Wang - San Jose CA, US
Allen Chang - Fremont CA, US
Man Sheng Hu - San Francisco CA, US
Xiaotian Zhang - San Jose CA, US
Assignee:
Alpha & Omega Semiconductor, Ltd - Hamilton
International Classification:
H01L 23/495
US Classification:
257676, 257666, 257686, 257780, 257781, 257E23031, 257E23039, 257E23059, 257E23079, 438123
Abstract:
A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

Lead Frame-Based Discrete Power Inductor

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US Patent:
7884696, Feb 8, 2011
Filed:
Jan 25, 2008
Appl. No.:
12/011489
Inventors:
François Hébert - San Mateo CA, US
Tao Feng - Santa Clara CA, US
Xiaotian Zhang - San Jose CA, US
Jun Lu - San Jose CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01F 5/00
US Classification:
336200
Abstract:
A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.

Stacked-Die Package For Battery Power Management

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US Patent:
7898092, Mar 1, 2011
Filed:
Nov 21, 2007
Appl. No.:
11/944313
Inventors:
Jun Lu - San Jose CA, US
Allen Chang - Fremont CA, US
Xiaotian Zhang - San Jose CA, US
Assignee:
Alpha & Omega Semiconductor, - Hamilton
International Classification:
H02H 9/00
US Classification:
257777, 257734, 257666, 257686, 257E23058, 257E25013
Abstract:
A stacked-die package for battery protection is disclosed. The battery protection package includes a power control integrated circuit (IC) stacked on top of integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs) or two discrete MOSFETs. The power control IC is either stacked on top of one MOSFET or on top of and overlapping both two MOSFETs.
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Xiaotian Zhang from Palo Alto, CA, age ~48 Get Report