Xiao Ying Zhang

8564049, Oct 22, 2013

Mar 31, 2008

11/894240

Ming Sun - Sunnyvale CA, US
Kai Liu - Sunnyvale CA, US
Xiao Tian Zhang - San Jose CA, US
Yueh Se Ho - Sunnyvale CA, US
Leeshawn Luo - Santa Clara CA, US

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

H01L 29/66

257329, 257600

This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

20060145319, Jul 6, 2006

Dec 31, 2004

11/027081

Ming Sun - Sunnyvale CA, US
Kai Liu - Sunnyvale CA, US
Xiao Zhang - San Jose CA, US
Yueh Ho - Sunnyvale CA, US
Leeshawn Luo - Santa Clara CA, US

H01L 23/02

257678000

This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

20120128017, May 24, 2012

Nov 17, 2011

13/299326

Claudia Felser - Dresden, DE
Shoucheng Zhang - Stanford CA, US
Xiao Zhang - Stanford CA, US

The Board of Trustees of the Leland Stanford Junior University - Stanford CA

H01S 5/323
H01L 33/30
H01L 31/0304
H01L 31/0248

372 4401, 257 14, 257 13, 257222, 257E33023, 257E31019

An electrical device includes a charge carrier transport layer formed using a ternary semiconducting compound having a stoichiometry of 1:1:1 and an element combination selected from the set of I-II-V, I-III-IV, II-II-IV, and I-I-VI; or having a stoichiometry of 3:1:2 and an element combination selected from the set of I-III-V; or having a stoichiometry of 2:1:1 and an element combination selected from the set of I-II-IV. In some embodiments, the charge carrier transport layer is used as the radiation absorption layer for a photovoltaic cell, or a light emitting layer of a light emitting device. Other devices, such as laser diode, a photodetection device, an optical modulator, a transparent electrode and a window layer, can also be formed using the ternary semiconducting compound as the charge carrier transport.

20120138887, Jun 7, 2012

Dec 6, 2011

13/312942

Shoucheng Zhang - Stanford CA, US
Xiao Zhang - Stanford CA, US

The Board of Trustees of the Leland Stanford Junior University - Stanford CA

H01L 29/06

257 9, 257E29005

An electrical device includes a current transport layer formed using a layer of a topological material selected from the group of a topological insulator, a quantum anomalous hall (QAH) insulator, a topological insulator variant, and a topological magnetic insulator. In one embodiment, the current transport layer forms a conductive wire on an integrated circuit where the conductive wire includes two spatially separated edge channels, each edge channel carrying charge carriers propagating in one direction only. In other embodiments, an optical device includes an optical layer formed using a layer of the topological material. The optical layer can be a light absorbing layer, a light emitting layer, a light transport layer, or a light modulation layer.

53176464, May 31, 1994

Mar 24, 1992

7/856434

Henry W. Sang - Cupertio CA
Xiao B. Zhang - Foster City CA

Xerox Corporation - Stamford CT

G06K 934
G06K 964
G06K 968
G06K 920

382 9

A forms recognition system having a method which assists an operator in creating an electronic template. The automated method would allow an operator to view an electronic bitmap of a master or blank form on a graphical display, the master form having bounded or semi-bounded regions depicting fields. An operator would display the bitmap, select a single point within a bounded or semi-bounded region on the bitmap with a pointing device, and the coordinates representing the bounded region would be automatically determined using the single point selected by the operator.

57712450, Jun 23, 1998

Mar 20, 1992

7/856001

Xiao Bei Zhang - Foster City CA

Xerox Corporation - Stamford CT

H03M 1300
G06F 1100

371 391

All error correction computations for correcting decode errors that corrupt a binary message that is encoded in a two dimensional code, such as a two dimensional self-clocking glyph code, are performed on byte aligned (or, more generally, symbol aligned) symbol sets that span the message but no other variables.

52451658, Sep 14, 1993

Dec 27, 1991

7/814841

Xiao B. Zhang - Foster City CA

Xerox Corporation - Stamford CT

G06K 710
G06K 1906

235454

A self-clocking glyph code is provided for encoding dual bit digital values in the cardinal rotations (0. degree. , 90. degree. , 180. degree. and 270. degree. ) of a logically ordered sequence of wedge-shaped glyphs that are written, printed, or otherwise recorded on a hardcopy recording medium in accordance with a predetermined spatial formatting rule. For example, these wedge-shaped glyphs suitably are essentially identical right triangles. The widths of such glyphs vary unidirectionally as a function of their height, so they can be decoded reliably, even when they are degraded by scan errors, dropped scan lines and/or random noise patterns. The decoding can be carried out in a variety of different ways, including by means of a bounding box analysis of the glyphs to determine whether the center of mass of each glyph is in the upper right, upper left, lower right or lower left quadrant of its bounding box; or by means of a bounding box analysis of the glyphs to determine whether the inclined surface of each wedge is on its right-hand side or its left-hand side and tilted to the right or left; or by means of a comparative run length analysis of each of the glyphs to determine whether its shortest run of adjacent ON pixels is spatially located above or below, and to the right or left of center of, its longest run of adjacent ON pixels.

20200090039, Mar 19, 2020

Nov 17, 2017

16/494842

- Mountain View CA, US
Yuan Li - Fremont CA, US
Bo Wu - Pleasanton CA, US
Chao-Yeh Chen - Mountain View CA, US
Xiao Zhang - Mountain View CA, US
Hartwig Adam - Marina del Rey CA, US

G06N 3/08
G06N 20/00
G06K 9/32

A computer-implemented method for generating a unified machine learning model using a neural network on a data processing apparatus is described. The method includes the data processing apparatus determining respective learning targets for each of a plurality of object verticals. The data processing apparatus determines the respective learning targets based on two or more embedding outputs of the neural network. The method also includes the data processing apparatus training the neural network to identify data associated with each of the plurality of object verticals. The data processing apparatus trains the neural network using the respective learning targets and based on a first loss function. The data processing apparatus uses the neural network trained to generate a unified machine learning model, where the model is configured to identify particular data items associated with each of the plurality of object verticals.