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Wooram N Lee

from State College, PA
Age ~46
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Also known as:
Lee Wooram, Ram Lee Woo
Related to:
Yong Ae Schnell, 80Sang Min Lee, 71Vivian Tang, 43Kwok Lee, 49Grace J Lee, 57Jin S Lee, 70Henry Lee, 54
Connected to:
Aarron Lee, 39Ada P Lee, 66Adam Y Lee, 63Adrienna V Lee, 57Aekyung P Lee, 66Aeron C Lee, 48Ahmed F Lee, 57Ahran Lee, 39Ahrom A Lee, 38Aiesha M Lee, 40

Wooram Lee Phones & Addresses

  • State College, PA
  • Briarcliff Manor, NY
  • Croton on Hudson, NY
  • Irvine, CA
  • Ithaca, NY
  • White Plains, NY

Resumes

Resumes

Wooram Lee Photo 1

Research Staff Member

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Location:
5b Olde Willow Way, Briarcliff Manor, NY 10510
Industry:
Semiconductors
Work:
Columbia University In the City of New York
Adjunct Professor
Ibm
Research Staff Member
Broadcom Mar 2014 - Feb 2015
Senior Scientist
Broadcom Jul 2012 - Feb 2014
Staff Scientist
Ibm May 2011 - Sep 2011
Research Intern
Education:
Cornell University 2007 - 2012
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy Korea Advanced Institute of Science and Technology 2001 - 2003
Master of Science, Masters, Electrical Engineering Korea Advanced Institute of Science and Technology 1997 - 2001
Bachelors, Bachelor of Science, Electrical Engineering Inchon Science High School
Skills:
Research
Semiconductors
Wooram Lee Photo 2

Wooram Lee

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Publications

Us Patents

Resonator Circuit And Amplifier Circuit

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US Patent:
20130207725, Aug 15, 2013
Filed:
Jun 7, 2011
Appl. No.:
13/702444
Inventors:
Ehsan Afshari - Ithaca NY, US
Wooram Lee - Ithaca NY, US
Assignee:
CORNELL UNIVERSITY - Ithaca NY
International Classification:
H03F 7/04
H03G 3/00
US Classification:
330278, 330144
Abstract:
A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. For example, one embodiment is a 20 GHz frequency divider utilizing a CMOS varactor and made in a 0.13 μm CMOS process. In this embodiment: (i) without any dc power consumption, 600 mV differential output amplitude can be achieved for an input amplitude of 600 mV; and (ii) the input frequency ranged from 18.5 GHz to 23.5 GHz with varactor tuning. In this embodiment, the output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. Also, a resonant parametric amplifier with a low noise figure (NF) by exploiting the noise squeezing effect. Noise squeezing occurs through the phase-sensitive amplification process and suppresses one of two quadrature components in input noise. When the input signal is only in the direction of the non-suppressed quadrature component, squeezing can lower that NF by almost 3 dB. The resonant structure of the proposed amplifier achieves the squeezing effect using a low number of LC elements.

Lo Leakage Suppression In Frequency Conversion Circuits

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US Patent:
20220231668, Jul 21, 2022
Filed:
Oct 14, 2021
Appl. No.:
17/501088
Inventors:
- Armonk NY, US
BODHISATWA SADHU - Peekskill NY, US
WOORAM LEE - BRIARCLIFF MANOR NY, US
International Classification:
H03H 11/32
H03D 7/14
H03B 5/12
Abstract:
A processor may calibrate a first actuator electrically coupled to a transconductance stage of the frequency conversion circuit. The transconductance stage may be configured to receive a differential signal input. Calibrating a first actuator may adjust a first basis vector associated with a differential direct current (DC) output of the transconductance stage. A processor may calibrate a second actuator electrically coupled to receive the differential current output of the transconductance stage and electrically coupled to a set of commutating devices of the frequency conversion circuit. The commutating devices may be configured to receive differential LO inputs. Calibrating a second actuator may adjust a second basis vector associated with a differential impedance of the set of commutating devices. A processor may offset responsive to adjusting the first basis vector and the second basis vector, the first leakage basis vector and second leakage basis vector of the LO leakage signal.

Circuit Methodology For Highly Linear And Symmetric Resistive Processing Unit

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US Patent:
20210151102, May 20, 2021
Filed:
Dec 30, 2020
Appl. No.:
17/137615
Inventors:
- Armonk NY, US
Seyoung Kim - White Plains NY, US
Hyung-Min Lee - YORKTOWN HEIGHTS NY, US
Wooram Lee - BRIARCLIFF MANOR NY, US
Paul Michael Solomon - Ossining NY, US
International Classification:
G11C 13/00
G11C 7/10
G11C 11/54
G06N 3/04
G06N 3/063
G06N 3/08
G06N 3/02
Abstract:
A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Digital Control Of A Voltage Controlled Oscillator Frequency

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US Patent:
20200259496, Aug 13, 2020
Filed:
Feb 7, 2019
Appl. No.:
16/270564
Inventors:
- Armonk NY, US
Bodhisatwa Sadhu - Peekskill NY, US
Wooram Lee - Briarcliff Manor NY, US
Daniel Friedman - Sleepy Hollow NY, US
International Classification:
H03L 7/099
H03B 5/12
H03L 7/10
Abstract:
A capacitance of a digitally controlled circuit coupled to a first multiplexer (MUX) having a first switch coupled between a first input and a first output, a first pullup device coupled between VDD and the first output, and a first pulldown device coupled between the first output and VSS is controlled. For falling slope of the first output, in a first phase, which is before the falling slope of the first output, turning ON the first switch, and turning OFF the first pullup device. In a second phase, which is during the falling slope of the first output, the first input is coupled to an output of a digital to analog converter coupled to the MUX. In a third phase, which is after the falling slope of the first output, the first switch is turned OFF and the first pulldown device is turned ON.

Scalable Phased Array Package

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US Patent:
20190260109, Aug 22, 2019
Filed:
Feb 21, 2018
Appl. No.:
15/901371
Inventors:
- Armonk NY, US
Wooram Lee - Briarcliff Manor NY, US
Duixian Liu - Scarsdale NY, US
Christian Wilhelmus Baks - Pleasant Valley NY, US
Alberto Valdes-Garcia - Chappaqua NY, US
International Classification:
H01Q 1/22
H01L 23/367
H01L 23/66
H01L 23/00
H05K 1/18
H01Q 23/00
H01Q 21/00
H01Q 21/06
Abstract:
Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.

Scalable Phased Array Package

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US Patent:
20190260138, Aug 22, 2019
Filed:
Feb 21, 2018
Appl. No.:
15/901400
Inventors:
- Armonk NY, US
Wooram Lee - Briarcliff Manor NY, US
Duixian Liu - Scarsdale NY, US
Christian Wilhelmus Baks - Pleasant Valley NY, US
Alberto Valdes-Garcia - Chappaqua NY, US
International Classification:
H01Q 21/06
H01L 23/367
H01L 23/66
H01L 23/00
H05K 1/18
H01L 21/56
H01Q 1/22
H01Q 23/00
Abstract:
Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.

Circuit Methodology For Highly Linear And Symmetric Resistive Processing Unit

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US Patent:
20190228823, Jul 25, 2019
Filed:
Mar 28, 2019
Appl. No.:
16/367497
Inventors:
- Armonk NY, US
Seyoung Kim - White Plains NY, US
Hyung-Min Lee - Yorktown Heights NY, US
Wooram Lee - Briarcliff Manor NY, US
Paul Michael Solomon - Ossining NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G11C 13/00
G06N 3/08
G06N 3/063
G06N 3/04
G11C 11/54
G11C 7/10
Abstract:
A processing unit, including a first circuit part, and a capacitor connected to the first circuit part. The capacitor is charged or discharged by the first circuit part.

Suppression Of Noise Up-Conversion Mechanisms In Lc Oscillators

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US Patent:
20190165796, May 30, 2019
Filed:
Nov 30, 2017
Appl. No.:
15/826875
Inventors:
- ARMONK NY, US
Daniel J. Friedman - Sleepy Hollow NY, US
Bodhisatwa Sadhu - Fishkill NY, US
Wooram Lee - BRIARCLIFF MANOR NY, US
International Classification:
H03L 7/099
H03B 5/12
H03L 7/10
Abstract:
A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.
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Wooram N Lee from State College, PA, age ~46 Get Report