William Ernest Nehrer

6734491, May 11, 2004

Dec 30, 2002

10/331705

Jozef C. Mitros - Richardson TX
Imran Khan - Richardson TX
William Nehrer - Soquel CA
Lou Hutter - Plano TX
Dirk Preikszat - Freising, DE

Texas Instruments Deutschland GmbH - Freising

H01L 29788

257315, 257316, 257317, 257321

A semiconductor device ( ) comprising a semiconductor substrate ( ) having source and drain regions ( ) located in the semiconductor substrate ( ) and having similar doping profiles, wherein a channel region ( ) extends from the source region ( ) to the drain region ( ). The semiconductor device ( ) also comprises a dielectric layer ( ) located over the source and drain regions ( ), the dielectric layer ( ) having first and second thicknesses (T , T ) wherein the second thickness (T ) is substantially less than the first thickness (T ) and is partially located over the channel region ( ). The semiconductor device ( ) also comprises a gate ( ) located over the dielectric layer ( ) wherein the second thickness (T ) is located between an end ( ) of the gate ( ) and one of the source and drain regions ( ).

6908859, Jun 21, 2005

Oct 8, 2002

10/267264

Sameer P. Pendharkar - Richardson TX, US
Taylor R. Efland - Richardson TX, US
William Nehrer - Soquel CA, US

Texas Instruments Incorporated - Dallas TX

H01L021/302

438689, 438527, 438228, 438247, 438252, 438224, 438687, 438688

A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

6979615, Dec 27, 2005

Sep 12, 2002

10/243405

Imran M. Khan - Richardson TX, US
Louis N. Hutter - Plano TX, US
James Todd - Plano TX, US
Jozef C. Mitros - Richardson TX, US
William E. Nehrer - Soquel CA, US

Texas Instruments Incorporated - Dallas TX

H01L021/336
H01L021/8242
H01L021/8234

438257, 438243, 438238

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

7279738, Oct 9, 2007

Jun 2, 2005

11/145460

Imran M. Khan - Richardson TX, US
Louis N. Hutter - Plano TX, US
James (Bob) Todd - Plano TX, US
Jozef C. Mitros - Richardson TX, US
William E. Nehrer - Soquel CA, US

Texas Instruments Incorporated - Dallas TX

H01L 29/788

257315, 257314, 257316, 438257, 438593

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

20030228764, Dec 11, 2003

Jun 5, 2002

10/163450

Imran Khan - Richardson TX, US
William Nehrer - Soquel CA, US
James Todd - Plano TX, US
Weidong Tian - Dallas TX, US
Louis Hutter - Plano TX, US

H01L021/302
H01L021/461

438/692000

The present invention relates to a method for forming an analog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.

20040175891, Sep 9, 2004

Mar 15, 2004

10/801760

Jozef Mitros - Richardson TX, US
Imran Khan - Richardson TX, US
William Nehrer - Soquel CA, US
Lou Hutter - Plano TX, US
Dirk Preikszat - Freising, DE

Texas Instruments Deutschland GmbH - Freising

H01L021/336
H01L021/8236

438/276000

A semiconductor device () comprising a semiconductor substrate () having source and drain regions () located in the semiconductor substrate () and having similar doping profiles, wherein a channel region () extends from the source region () to the drain region (). The semiconductor device () also comprises a dielectric layer () located over the source and drain regions (), the dielectric layer () having first and second thicknesses (T, T) wherein the second thickness (T) is substantially less than the first thickness (T) and is partially located over the channel region (). The semiconductor device () also comprises a gate () located over the dielectric layer () wherein the second thickness (T) is located between an end () of the gate () and one of the source and drain regions ().

20230106522, Apr 6, 2023

Oct 1, 2021

17/491778

- Santa Clara CA, US
William NEHRER - Soquel CA, US
Jungwon PARK - San Jose CA, US

C23C 16/44
C23C 16/52

Embodiments of the present disclosure relate to a shadow frame support with one or more flow controllers and a method of controlling the flow of gases through the shadow frame support. The shadow frame support includes a body coupled to walls of a chamber such that a top surface of the shadow frame support is horizontally disposed in the chamber. The body has a plurality of channels disposed therethrough. Each channel includes a flow controller. The flow controller may be adjusted in real-time to change the open ratio of the flow controller.