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William Chris Moyes

from Leander, TX
Age ~40
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Also known as:
William C Moyes, Chris Moyes
Phone and address:
4413 Trinity Woods St, Leander, TX 78641
Related to:
Kylie Moyes, 32Chaelee M MoyesStephen J Ehrler, 40Joe L Ehrler, 79Ashley L Newton, 38Thomas C Moyes, 41Tamra J Moyes, 66Jennifer K Moyes, 40Ernestina R Ehrler, 78
Connected to:
David H Moyes, 76Gwen A Moyes, 73Hsiou C Moyes, 58Jayne D Moyes, 25Joanna L Moyes, 43Jonathan J Moyes, 37Kevin W Moyes, 59Kirk R Moyes, 60Laura J Moyes, 97Lucinda Moyes, 66

William Moyes Phones & Addresses

  • 4413 Trinity Woods St, Leander, TX 78641
  • 5800 Brodie St, Austin, TX 78745 (512) 899-8381
  • Cedar Park, TX
  • Lubbock, TX
  • Longview, TX

Resumes

Resumes

William Moyes Photo 1

Server Firmware Architect

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Location:
Austin, TX
Industry:
Computer Hardware
Work:
Amd
Server Firmware Architect
Ocarina Networks Aug 2011 - Jan 2017
Bios Engineer
Amd May 2001 - Aug 2011
Bios Engineer and Team Lead
Wayforward Technologies 1995 - 1996
Programmer
Education:
Brigham Young University 1998 - 2001
Bachelors, Bachelor of Science, Computer Science
Skills:
Firmware
X86
Processors
Debugging
Computer Architecture
Hardware Architecture
Microprocessors
Bios
Device Drivers
Embedded Systems
Semiconductors
X86 Assembly
Perl
Embedded Software
C++
Usb
Software Engineering
Virtualization
Soc
Pcie
Microcontrollers
William Moyes Photo 2

Inside Sales Representative

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Location:
San Diego, CA
Industry:
Marketing And Advertising
Work:
Gompers Preparatory Academy Aug 2017 - Oct 2018
Teacher on Staff
Closingcorp Aug 2017 - Oct 2018
Inside Sales Representative
Education:
San Diego Christian College 2016 - 2017
San Diego State University 2014 - 2016
Bachelors, Social Sciences
Skills:
Microsoft Excel
Salesforce.com
Sales
Customer Satisfaction
Microsoft Office
Microsoft Word
Teaching
Management
Account Management

Publications

Wikipedia

David Moyes

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David William Moyes (born 25 April 1963, in Glasgow, Scotland) is an association football manager and former player, currently managing English Premier ...

Us Patents

Simultaneous Multiprocessor Memory Testing And Initialization

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US Patent:
7065688, Jun 20, 2006
Filed:
Feb 19, 2003
Appl. No.:
10/370325
Inventors:
William A. Moyes - Austin TX, US
Michael V. Mattress - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 29/00
US Classification:
714718, 714 25, 706 42, 700 2
Abstract:
In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality of processing nodes, a technique is presented that allows each of the plurality of processing nodes to perform a memory initialization and test of the processing node's assigned portion of system memory. One of the processing nodes can cause the others of the processing nodes to perform the memory initialization and test process or each processing node can automatically perform the memory initialization and test process.

Communication Network Initialization Using Graph Isomorphism

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US Patent:
20090016355, Jan 15, 2009
Filed:
Jul 13, 2007
Appl. No.:
11/777727
Inventors:
William A. Moyes - Austin TX, US
International Classification:
H04L 12/56
US Classification:
37039531
Abstract:
A communication system, such as a computer system, with a plurality of processing nodes coupled by communication links stores a database of abstract topologies that provides a node adjacency matrix and abstract routing between nodes. A breadth-first discovery of the actual communication fabric is performed starting from an arbitrary root node to discover the actual topography. A graph isomorphism algorithm finds a match between the discovered topology and one of the stored abstract topologies. The graph isomorphism algorithm provides a mapping between the ‘abstract’ node numbers and the discovered node numbers. That mapping may be used to rework the stored routing tables into the specific format needed. The computed routing tables are loaded into the fabric starting at the leaf nodes, working back towards the root node (i.e., start loading from the highest node number and work back to the lowest numbered node).

Optimized Thread Scheduling Via Hardware Performance Monitoring

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US Patent:
20110055838, Mar 3, 2011
Filed:
Aug 28, 2009
Appl. No.:
12/549701
Inventors:
William A. Moyes - Austin TX, US
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
A system and method for efficient dynamic scheduling of tasks. A scheduler within an operating system assigns software threads of program code to computation units. A computation unit may be a microprocessor, a processor core, or a hardware thread in a multi-threaded core. The scheduler receives measured data values from performance monitoring hardware within a processor as the one or more processors execute the software threads. The scheduler may be configured to reassign a first thread assigned to a first computation unit coupled to a first shared resource to a second computation unit coupled to a second shared resource. The scheduler may perform this dynamic reassignment in response to determining from the measured data values a first measured value corresponding to the utilization of the first shared resource exceeds a predetermined threshold and a second measured value corresponding to the utilization of the second shared resource does not exceed the predetermined threshold.

System And Method For Providing Fine-Grained Memory Cacheability During A Pre-Os Operating Environment

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US Patent:
20180373543, Dec 27, 2018
Filed:
Jun 22, 2017
Appl. No.:
15/630511
Inventors:
- Round Rock TX, US
Juan F. Diaz - Round Rock TX, US
William A. Moyes - Austin TX, US
International Classification:
G06F 9/44
G06F 12/1009
G06F 9/30
Abstract:
An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

Synchronizing A Cursor From A Managed System With A Cursor From A Remote System

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US Patent:
20160320942, Nov 3, 2016
Filed:
Jul 15, 2016
Appl. No.:
15/211572
Inventors:
- Round Rock TX, US
William A. Moyes - Austin TX, US
International Classification:
G06F 3/0481
G06F 9/44
G06F 3/14
Abstract:
A method includes receiving reports of the pointing device events occurring on a remote computer at a host computer and performing computations in the host computer based upon the mouse reports. The method includes generating screen images in the host computer based upon the computations, the screen images not containing images of a cursor representing locations pointed to by a pointing device of the host computer. The generated screen images are transmitted to the remote computer. In some embodiments, the reports may be received by a remote console controller. An information handling system includes boot firmware to set a mouse to operate in absolute mode under control of the boot firmware. An information handling system separately transmits to a remote console controller of the information handling system screen images without a cursor and cursor images.

Uefi Virtual Video Controller

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US Patent:
20160314758, Oct 27, 2016
Filed:
Apr 27, 2015
Appl. No.:
14/697057
Inventors:
- Round Rock TX, US
William A. Moyes - Austin TX, US
International Classification:
G09G 5/00
G06F 13/362
G06F 13/28
Abstract:
An information handling system includes a processor; a memory, a firmware, and a video agent. The memory includes a frame buffer for image data. The frame buffer accessible to an operating system. The firmware is configured to present to the operating system a graphics output protocol. The graphics output protocol includes an address of the portion of the reserved portion of the memory and soft video display parameters. The video agent is configured to retrieve image data from the reserved portion of the memory, and provide the image data to an external system for remote video display to be completed upon finalization of application.

Synchronizing A Cursor From A Managed System With A Cursor From A Remote System

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US Patent:
20140204026, Jul 24, 2014
Filed:
Jan 18, 2013
Appl. No.:
13/744978
Inventors:
- Round Rock TX, US
William A. Moyes - Austin TX, US
Assignee:
DELL PRODUCTS, LP - Round Rock TX
International Classification:
G06F 3/0354
US Classification:
345158
Abstract:
A method includes receiving reports of the pointing device events occurring on a remote computer at a host computer and performing computations in the host computer based upon the mouse reports. The method includes generating screen images in the host computer based upon the computations, the screen images not containing images of a cursor representing locations pointed to by a pointing device of the host computer. The generated screen images are transmitted to the remote computer. In some embodiments, the reports may be received by a remote console controller. An information handling system includes boot firmware to set a mouse to operate in absolute mode under control of the boot firmware. An information handling system separately transmits to a remote console controller of the information handling system screen images without a cursor and cursor images.

Isbn (Books And Publications)

The Banner Book: A Study of the Banners of the Lodges of Durham Miners' Association

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Author

William A. Moyes

ISBN #

0859830853

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William Chris Moyes from Leander, TX, age ~40 Get Report