William A Lynch

20130013888, Jan 10, 2013

Jul 3, 2012

13/541287

HoYu Lam - Brooklyn NY, US
Sailesh Kumar - San Jose CA, US
William Lynch - Los Altos CA, US

FUTUREWEI TECHNOLOGIES, INC. - Plano TX

G06F 12/10

711206, 711E12061

An apparatus comprising a memory configured to store a routing table and a processor coupled to the memory, the processor configured to generate a request to access at least a section of an instance, assign an index to the request based on the instance, lookup an entry in the routing table based on the index, wherein the entry comprises a resource bit vector, and identify a resource comprising at least part of the section of the instance based on the resource bit vector.

53731808, Dec 13, 1994

Sep 14, 1993

8/121082

Steven J. Hillenius - Summit NJ
William T. Lynch - Summit NJ
Lalita Manchanda - New Providence NJ
Mark R. Pinto - Morristown NJ
Sheila Vaidya - Watchung NJ

AT&T Corp. - Murray Hill NJ

H01L 2704

257357

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e. g. , design rules of 0. 9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e. g. , field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

47660902, Aug 23, 1988

Nov 21, 1986

6/933631

Gerald A. Coquin - New Providence NJ
William T. Lynch - Summit NJ
Louis C. Parrillo - Warren NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H01L 21425

437 57

A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10. mu. m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

46461230, Feb 24, 1987

Apr 21, 1986

6/857391

William T. Lynch - Summit NJ
Louis C. Parrillo - Warren NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2702
H01L 2906

357 42

A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10. mu. m, as well as a method for fabricating the device, is disclosed. The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10. mu. m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

48252786, Apr 25, 1989

Mar 2, 1987

7/020771

Steven J. Hillenius - Summit NJ
William T. Lynch - Summit NJ
Lalita Manchanda - North Plainfield NJ

American Telephone and Telegraph Company AT&T Bell Laboratories - Murray Hill NJ

H01L 2940

357 53

Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.

44855508, Dec 4, 1984

Jul 23, 1982

6/401142

Conrad J. Koeneke - Fanwood NJ
Martin P. Lepselter - Summit NJ
William T. Lynch - Summit NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2128

29571

Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).

50574558, Oct 15, 1991

Nov 30, 1989

7/443766

William T. Lynch - Summit NJ
Chien-Shing Pai - Bridgewater NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 21283

437193

In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an. alpha. -amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors. In addition, both the source and drain electrodes of the MOS transistors and the base electrodes of the bipolar transistors can then be simultaneously formed in a self-aligned manner without the need for etching into the underlying semiconductor substrate in which the integrated circuit is being formed.

46438041, Feb 17, 1987

Jul 25, 1985

6/758797

William T. Lynch - Summit NJ
Thomas E. Seidel - Carlsbad CA

AT&T Bell Laboratories - Murray Hill NJ

C25D 1102

204 15

Selective wet or plasma anodization is utilized for forming a relatively thick dielectric layer only at the bottoms of trenches included in DRAM and/or CMOS devices. In that way, the electrical characteristics of trenches that include bottoms having surface roughness and/or sharp or irregular corners are significantly improved. Additionally, electrically isolated capacitor structures in elongated trenches formed in DRAM devices are thereby made feasible.