Resumes
Resumes
William Gouin Phones & Addresses
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309 Wyant Ln, Hamilton, MT 59840 (406) 363-5054
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16820 Bohlman Rd, Saratoga, CA 95070 (408) 867-6665
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Aaronsburg, PA
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San Jose, CA
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Santa Clara, CA
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16820 Bohlman Rd, Saratoga, CA 95070 (408) 804-1880
Work
Position:
Food Preparation and Serving Related Occupations
Education
Degree:
High school graduate or higher
Emails
Publications
Us Patents
Electrolytic Chromium Etching Of Chromium-Layered Semiconductor
View pageUS Patent:
40789802, Mar 14, 1978
Filed:
Oct 1, 1976
Appl. No.:
5/728575
Inventors:
James M. Harris - San Jose CA
William M. Gouin - San Jose CA
Bruce Gray - Sunnyvale CA
William M. Gouin - San Jose CA
Bruce Gray - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
C25F 312
C25F 500
C25F 500
US Classification:
2041293
Abstract:
A layer of chromium is removed from the metalization system on a silicon integrated circuit wafer that also includes copper and aluminum. By electrolytic etching in a sulfuric acid solution containing about 10% by volume water saturated with chromium sulfate, chromium can be removed without excessive removal of copper or aluminum.
Method For Gold Plating Of Metallic Layers On Semiconductive Devices
View pageUS Patent:
40054721, Jan 25, 1977
Filed:
May 19, 1975
Appl. No.:
5/578651
Inventors:
James M. Harris - San Jose CA
William M. Gouin - San Jose CA
William M. Gouin - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2946
H01L 2348
H01L 2348
US Classification:
357 71
Abstract:
An integrated circuit semiconductive device has a plurality of copper gang bonding bumps formed on the upper surface thereof. The bumps rise substantially above the surface of the semiconductive device and serve to make electrical connection to a pattern of intraconnect metallization formed on the semiconductive device for making electrical contact to various regions within the semiconductive body of the integrated circuit. The gang bonding bumps are to be thermal compression bonded to metallic leads by an automatic bonding machine. As a final step to the processing of the semiconductive wafers, containing the individual semiconductive devices, the wafers are immersed in an immersion gold plating solution for plating an antioxidant protective coating of gold of a thickness less than 6000 angstroms onto the copper gang bonding bumps to prevent oxidation thereof either before or during the gang bonding step. The thickness of such gold antioxidant coating permitting thermal compression bonding therethrough to the underlying metal layer.
Raised Bonding Pad
View pageUS Patent:
42688493, May 19, 1981
Filed:
Nov 3, 1978
Appl. No.:
5/957645
Inventors:
Bruce Gray - Southbury CT
James M. Harris - Palo Alto CA
William M. Gouin - San Jose CA
James M. Harris - Palo Alto CA
William M. Gouin - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2348
US Classification:
357 71
Abstract:
A bonding pad structure for an LED includes a first layer of nickel-chromium in contact with the contact face of a gallium arsenide wafer with further layers of either gold, palladium, or both, with palladium being the top layer of the first pad structure laid down by vaporization with a raised structure overlying the first structure by means of plating and including layers of nickel, gold and/or other conducting metal.