William L Devanney

6763406, Jul 13, 2004

Feb 1, 2001

09/775428

William L. Devanney - Menlo Park CA
Robert J. Proebsting - Los Altos Hills CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1312

710 65, 710 33, 709246, 712223

A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word. The complement next data word is instead communicated onto the bus along with an indicator signal to indicate that a complement data word is communicated onto the bus.

20030200520, Oct 23, 2003

Aug 24, 2001

09/939015

Alan Huggins - Gilroy CA, US
David Schmulian - San Jose CA, US
John MacPherson - Fremont CA, US
William Devanney - Menlo Park CA, US

G06F017/50

716/016000, 716/017000

Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device. A computer-based apparatus is also provided for decoding a bitstream that characterizes the programmable logic device having a first operational functionality when programmed, into a netlist that designates electrical connections in the gate array device when wired to have the first operational functionality, and to provide a method for generating scan-based test vectors to verify the first functionality. Accordingly, when switching from a functional programmable logic device (PLD) implementation to a gate array implementation, it is unnecessary to start the design process over from scratch by performing logic synthesis, place and route and other front end design operations associated with conventional gate array design techniques.

62256521, May 1, 2001

Aug 2, 1999

9/365494

William L. Devanney - Menlo Park CA

Clear Logic, Inc. - San Jose CA

H01L 2710

257209

A laser fuse structure and array are provided which use vertical vias to connect the fuse body of the laser fuse to an interconnect layer. The vias extend downward from the fuse body and thus require less layout area. The thermal conductivity of the vias are minimized by restricting their cross-sectional area and by using tungsten as the via fill material. In some embodiments, an underlying conductive line is widened to minimize damage to the line during lasering. In another embodiment, the width of the fuse body is increased to reduce the energy required to blow the fuse. As a result, unrelated circuit elements and patterned lines can be placed closer together in a laser fuse array, thereby increasing the packing density of such arrays.

55418830, Jul 30, 1996

May 9, 1995

8/437534

William L. Devanney - Pacific Grove CA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 700

365201

A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a "long write" test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM. In one embodiment, a multiple column select circuit includes an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of the static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V. sub. DD to ground potential thereby simultaneously selecting multiple columns of the static RAM. In another embodiment, a multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby selecting all columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit to select only one column.

54405246, Aug 8, 1995

Feb 1, 1994

8/190806

William L. Devanney - Pacific Grove CA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 800

36523006

A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a "long write" test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM. In one embodiment, a multiple column select circuit includes an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of the static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V. sub. DD to ground potential thereby simultaneously selecting multiple columns of the static RAM. In another embodiment, a multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby selecting all columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit to select only one column.

59109220, Jun 8, 1999

Aug 5, 1997

8/906448

Alan H. Huggins - Gilroy CA
William L. Devanney - Menlo Park CA
Chuen-Der Lien - Los Altos Hills CA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 700

365201

A circuit and a method for providing a power supply voltage to a memory circuit during a memory data retention test are provided. In such a circuit, a first power supply terminal and a second power supply terminal are provided together with a plurality of circuit elements, which are coupled to form a current path between the first and second power supply terminals, such that each circuit element contributes a predetermined voltage drop between the first and second power supply terminals when a current flows in said current path. In addition, a shunt device having a control terminal and coupled across one or more of said circuit elements is provided. The control terminal receives a control signal, such that when the control signal is asserted, the shunt device equalizes a voltage across said one or more of said circuit elements. The memory circuit draws its power supply voltage from the second power supply terminal.

62437798, Jun 5, 2001

Nov 21, 1996

8/755542

William L. Devanney - Menlo Park CA
Robert J. Proebsting - Los Altos Hill CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1336
G06F 300
H03K 19003
H03K 190175

710129

A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word. The complement next data word is instead communicated onto the bus along with an indicator signal to indicate that a complement data word is communicated onto the bus.

61916412, Feb 20, 2001

Feb 23, 1999

9/255967

William L. Devanney - Menlo Park CA

Clear Logic, Inc. - San Jose CA

H01H 3776

327525

A zero static power laser fuse circuit is formed from one laser fuse and three transistors, with the fuse connected in series to a reverse-biased diode and with the common node of the fuse and diode connected to the input of a driving circuit, such as a CMOS inverter. Blowing the fuse allows a small subthreshold conduction current to flow to the common node and pull the node to the opposite logic state. This fuse circuit, which allows the capacitance at the common node to be minimized for zero static power operation, requires less circuit area than previous zero static power fuse circuits.