Walter A Wohlmuth

6697412, Feb 24, 2004

Apr 13, 2001

09/834832

Gary A. Evans - Plano TX
Paul Saunier - Addison TX
Ming-Yih Kao - Dallas TX
David M. Fanning - Garland TX
William H. Davenport - Hillsboro OR
Andy Turudic - Hillsboro OR
Walter A. Wohlmuth - Hillsboro OR

TriQuint Semiconductor, Inc. - Hillsboro OR

H01S 5183

372 96, 257190, 372 45

A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1. 3 microns to about 1. 55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.

7368980, May 6, 2008

Apr 25, 2005

11/114642

Rebouh Benelbar - Murphy TX, US
Walter Wohlmuth - Portland OR, US

TriQuint Semiconductor, Inc. - Hillsboro OR

G05F 1/10

327538, 327546

An exemplary circuit embodiment includes a depletion-mode transistor and an enhancement-mode transistor. The circuit also includes a circuit portion coupled to a gate region of the depletion-mode transistor and to a gate region of the enhancement-mode transistor. In this embodiment, the circuit portion is configured to provide a reference voltage at an output node, wherein the reference voltage is associated with a difference between a voltage at the gate region of the depletion-mode transistor and a voltage at the gate region of the enhancement-mode transistor.

7449728, Nov 11, 2008

Nov 24, 2003

10/721437

Walter Anthony Wohlmuth - Portland OR, US

Tri Quint Semiconductor, Inc. - Hillsboro OR

H01L 31/072
H01L 31/0328

257192, 257155, 257195, 257392, 257E21047, 257E21631

A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.

7655546, Feb 2, 2010

Oct 11, 2005

11/248935

Walter Anthony Wohlmuth - Portland OR, US

TriQuint Semiconductor, Inc. - Hillsboro OR

H01L 27/02
H01L 31/072

438576, 438167, 438172, 438570, 438572, 438573, 257155, 257191, 257192, 257E27068, 257E29041

A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.

20060197129, Sep 7, 2006

Mar 3, 2005

11/073330

Walter Wohlmuth - Portland OR, US

H01L 29/94

257296000

One embodiment of a fin-field effect transistor includes a material stack including a non-inverting su surface channel, a fin of semiconductor material positioned on the material stack, the fin including first and second opposing side surfaces, and a gate electrode positioned on the first and second opposing side surfaces of the fin.

20070023901, Feb 1, 2007

Jul 29, 2005

11/192915

Gerard Mahoney - Hillsboro OR, US
Matthew Essar - Hillsboro OR, US
Walter Wohlmuth - Hillsboro OR, US
Wayne Struble - Hillsboro OR, US

H01L 23/48

257736000

One embodiment of an integrated circuit includes a substrate, an electrical device positioned above the substrate, and a bond bad positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.