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Victor W So

from San Francisco, CA
Age ~75
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Also known as:
Wai Yan So, Wai S So, Wai Y So, Lau Lin So, Lau L So, Ujai Yan So, So W Yan, Waivan So, Laulin So, Wai Yanso
Related to:
Ka Yan Ho, 47
Connected to:
Aileen So, 59Alyssa P So, 28Arlington G So, 47Bao P So, 40Bella T So, 75Bernice C So, 40Billy So, 70Bryan G So, 47Caroline G So, 39Cecilia K So, 35

Victor So Phones & Addresses

  • San Francisco, CA
  • 1583 Chandler St, Oakland, CA 94603
  • Emeryville, CA
  • San Jose, CA
  • Alameda, CA
  • 2331 Holland St, San Mateo, CA 94403
  • San Leandro, CA

Specialities

Intellectual Property • Regulatory Law • Health Law • Administrative Law • Civil and Commercial Litigation

Professional Records

Lawyers & Attorneys

Victor So Photo 1

Victor So - Lawyer

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Specialties:
Intellectual Property
Regulatory Law
Health Law
Administrative Law
Civil and Commercial Litigation
ISLN:
919872385
Admitted:
2008
University:
University of Toronto, 2001; University of Toronto, 2001; University of Western Ontario, M.B.A., 2007
Law School:
University of Western Ontario, J.D., 2007

Resumes

Resumes

Victor So Photo 2

Victor So

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Location:
3901 north 1St St, San Jose, CA 95113
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation Feb 2001 - Jun 2013
Principal Application Engineer at Cypress Semiconductor
Zilog Feb 1986 - Feb 2001
Product Marketing Manager
Education:
National Tsing Hua University
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Ic
Semiconductors
Usb
Start Ups
Touch Interfaces
Firmware
Victor So Photo 3

Victor So

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Victor So Photo 4

Financial Associate At Citibank

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Location:
San Francisco Bay Area
Industry:
Banking

Publications

Us Patents

Simultaneously Driving A Hardware Device And A Software Model During A Test

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US Patent:
7017097, Mar 21, 2006
Filed:
Sep 24, 2002
Appl. No.:
10/253960
Inventors:
Michael T. Moore - Mountain View CA, US
Victor So - San Jose CA, US
Pankaj K. Jha - Fremont CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G01R 31/28
US Classification:
714742
Abstract:
An apparatus generally comprising a circuit and an interface device is disclosed. The circuit may be configured to (i) generate a plurality of test signals to simultaneously stimulate a device and a model of the device during a test and (ii) receive a plurality of model signals generated by the model in response to the test signals. The interface device may be configured to receive a plurality of device signals generated by the device in response the test signals.

Power Supply Interruption Detection And Response System For A Microcontroller

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US Patent:
54282527, Jun 27, 1995
Filed:
Jan 3, 1992
Appl. No.:
7/817465
Inventors:
Andre B. Walker - Los Gatos CA
Victor So - San Jose CA
Assignee:
Zilog, Inc. - Campbell CA
International Classification:
H02J 900
G11C 1400
US Classification:
307 64
Abstract:
A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ("CPU") receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored. This is particularly useful for battery operated systems, responding to both a low battery voltage condition and to a complete loss of power during battery replacement.
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Victor W So from San Francisco, CA, age ~75 Get Report