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Vladislav V Petkov

from Campbell, CA
Age ~43
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Also known as:
Vladislav C Petkov, Vladisla V Petkov, Valdislav Petkov, Vladislav Petrov
Phone and address:
1081 Shadle Ave, Campbell, CA 95008
Related to:
Shirley M Taylor, 88
Connected to:
Boriana P Petkova, 51Dimo Z Petkov, 53Lyubomir Petkov, 64Mariela Petkova, 35Mariyana G Petkova, 44Mike Petkov, 39Paulina Petkova, 33Pavlin M Petkov, 41Pepi E Petkov, 65Peter J Petkov, 77

Vladislav Petkov Phones & Addresses

  • 1081 Shadle Ave, Campbell, CA 95008
  • 400 Mclaughlin Dr, Santa Cruz, CA 95064
  • Fremont, CA

Publications

Us Patents

Methods And Apparatus For Verifying Completion Of Groups Of Data Transactions Between Processors

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US Patent:
20200210224, Jul 2, 2020
Filed:
Mar 9, 2020
Appl. No.:
16/813407
Inventors:
- Cupertino CA, US
Saurabh Garg - San Jose CA, US
Vladislav V. Petkov - Cupertino CA, US
International Classification:
G06F 9/46
G06F 9/54
Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Methods And Apparatus For Synchronizing Uplink And Downlink Transactions On An Inter-Device Communication Link

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US Patent:
20200174953, Jun 4, 2020
Filed:
Feb 3, 2020
Appl. No.:
16/780743
Inventors:
- Cupertino CA, US
Vladislav Petkov - Campbell CA, US
Radha Kumar Pulyala - Santa Clara CA, US
Saurabh Garg - San Jose CA, US
Haining Zhang - Cupertino CA, US
International Classification:
G06F 13/28
G06F 13/40
Abstract:
Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Methods And Apparatus For Verifying Completion Of Groups Of Data Transactions Between Processors

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US Patent:
20200034186, Jan 30, 2020
Filed:
Jul 30, 2018
Appl. No.:
16/049624
Inventors:
- Cupertino CA, US
Saurabh Garg - San Jose CA, US
Vladislav V. Petkov - Cupertino CA, US
International Classification:
G06F 9/46
G06F 9/54
Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Methods And Apparatus For Reduced Overhead Data Transfer With A Shared Ring Buffer

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US Patent:
20200026668, Jan 23, 2020
Filed:
Sep 30, 2019
Appl. No.:
16/588557
Inventors:
- Cupertino CA, US
Saurabh Garg - San Jose CA, US
Vladislav V. Petkov - Campbell CA, US
International Classification:
G06F 13/16
G06F 12/0831
G06F 15/167
G06F 15/173
Abstract:
Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

Memory Access Protection Apparatus And Methods For Memory Mapped Access Between Independently Operable Processors

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US Patent:
20190155757, May 23, 2019
Filed:
Jan 28, 2019
Appl. No.:
16/259543
Inventors:
- Cupertino CA, US
Karan Sanghi - Cupertino CA, US
Vladislav Petkov - Cupertino CA, US
Haining Zhang - Cupertino CA, US
International Classification:
G06F 12/14
G06F 12/1081
Abstract:
Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

Methods And Apparatus For Synchronizing Uplink And Downlink Transactions On An Inter-Device Communication Link

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US Patent:
20190034368, Jan 31, 2019
Filed:
Aug 6, 2018
Appl. No.:
16/056374
Inventors:
- Cupertino CA, US
Vladislav Petkov - Campbell CA, US
Radha Kumar Pulyala - Santa Clara CA, US
Saurabh Garg - San Jose CA, US
Haining Zhang - San Jose CA, US
International Classification:
G06F 13/28
G06F 13/40
Abstract:
Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Methods And Apparatus For Providing Access To Peripheral Sub-System Registers

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US Patent:
20180129261, May 10, 2018
Filed:
Jul 11, 2017
Appl. No.:
15/647088
Inventors:
- Cupertino CA, US
Karan Sanghi - Cupertino CA, US
Vladislav Petkov - Cupertino CA, US
Richard Solotke - Cupertino CA, US
International Classification:
G06F 1/32
G06F 9/30
Abstract:
Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Methods And Apparatus For Providing Individualized Power Control For Peripheral Sub-Systems

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US Patent:
20180129269, May 10, 2018
Filed:
Jul 11, 2017
Appl. No.:
15/647063
Inventors:
- Cupertino CA, US
Karan Sanghi - Cupertino CA, US
Vladislav Petkov - Cupertino CA, US
Richard Solotke - Cupertino CA, US
International Classification:
G06F 1/32
G06F 9/44
Abstract:
Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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Vladislav V Petkov from Campbell, CA, age ~43 Get Report