Resumes
Resumes
Vladimir Zlatkovic Phones & Addresses
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159 Common St, Belmont, MA 02478 (617) 484-0323
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57 Grant Ave, Watertown, MA 02472
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111 Broadmeadow St, Marlborough, MA 01752 (508) 485-1817 (978) 753-9979
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79 Park Ave, Worcester, MA 01605 (508) 753-9979
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Fall River, MA
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North Dartmouth, MA
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New Bedford, MA
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South Dennis, MA
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Publications
Us Patents
Storage Devices With Soft Processing
View pageUS Patent:
8107306, Jan 31, 2012
Filed:
Aug 6, 2009
Appl. No.:
12/537081
Inventors:
Benjamin Vigoda - Winchester MA, US
Eric Nestler - Concord MA, US
Jeffrey Bernstein - Middleton MA, US
David Reynolds - Scarborough ME, US
Alexander Alexeyev - Gorham ME, US
Jeffrey Venuti - Somerville MA, US
William Bradley - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Eric Nestler - Concord MA, US
Jeffrey Bernstein - Middleton MA, US
David Reynolds - Scarborough ME, US
Alexander Alexeyev - Gorham ME, US
Jeffrey Venuti - Somerville MA, US
William Bradley - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G11C 7/00
US Classification:
365191, 365198, 36518915, 36518917
Abstract:
A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
Storage Devices With Soft Processing
View pageUS Patent:
8179731, May 15, 2012
Filed:
Aug 6, 2009
Appl. No.:
12/537045
Inventors:
Benjamin Vigoda - Winchester MA, US
Eric Nestler - Concord MA, US
Jeffrey Bernstein - Middleton MA, US
David Reynolds - Scarborough ME, US
Alexander Alexeyev - Gorham ME, US
Jeffrey Venuti - Somerville MA, US
William Bradley - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Eric Nestler - Concord MA, US
Jeffrey Bernstein - Middleton MA, US
David Reynolds - Scarborough ME, US
Alexander Alexeyev - Gorham ME, US
Jeffrey Venuti - Somerville MA, US
William Bradley - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G11C 7/00
US Classification:
36518915, 365198
Abstract:
A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
Analog Computation
View pageUS Patent:
8188753, May 29, 2012
Filed:
Aug 21, 2009
Appl. No.:
12/545590
Inventors:
Eric Nestler - Harvard MA, US
Vladimir Zlatkovic - Belmont MA, US
Vladimir Zlatkovic - Belmont MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G01R 27/26
US Classification:
324658
Abstract:
Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.
Charge Sharing Analog Computation Circuitry And Applications
View pageUS Patent:
8547272, Oct 1, 2013
Filed:
Aug 18, 2011
Appl. No.:
13/813101
Inventors:
Eric Nestler - Concord MA, US
Vladimir Zlatkovic - Belmont MA, US
Jeffrey Venuti - Bedford MA, US
Vladimir Zlatkovic - Belmont MA, US
Jeffrey Venuti - Bedford MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03M 1/12
US Classification:
341172, 341155
Abstract:
In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e. g. , after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
Dual Path Linear Voltage Regulator
View pageUS Patent:
20080054861, Mar 6, 2008
Filed:
Sep 6, 2006
Appl. No.:
11/516214
Inventors:
Vladimir Zlatkovic - Belmont MA, US
International Classification:
G05F 1/10
US Classification:
323234
Abstract:
A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than −90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.
Charge Sharing Time Domain Filter
View pageUS Patent:
20120306569, Dec 6, 2012
Filed:
Jun 6, 2012
Appl. No.:
13/490110
Inventors:
Eric Nestler - Concord MA, US
Jeffrey Venuti - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Kartik Nanda - Cambridge MA, US
Jeffrey Venuti - Somerville MA, US
Vladimir Zlatkovic - Belmont MA, US
Kartik Nanda - Cambridge MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 5/00
US Classification:
327551
Abstract:
An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
Analog Computation
View pageUS Patent:
20130080497, Mar 28, 2013
Filed:
May 29, 2012
Appl. No.:
13/482112
Inventors:
Eric Nestler - Harvard MA, US
Vladimir Zlatkovic - Belmont MA, US
Vladimir Zlatkovic - Belmont MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G06F 17/14
US Classification:
708821
Abstract:
Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.
Duty Cycle Adjustment Circuit With Independent Range And Step Size Control
View pageUS Patent:
20220247398, Aug 4, 2022
Filed:
Feb 2, 2022
Appl. No.:
17/591520
Inventors:
- Mountain View CA, US
David Da-Wei LIN - Westborough MA, US
Vladimir ZLATKOVIC - Belmont MA, US
Shefali WALIA - Boxborough MA, US
Youssef Mamdouh EL-TOUKHY - Cairo, EG
Abdelrahman Alaa GOUDA - Cairo, EG
Alexander A. ALEXEYEV - Beverly MA, US
David Da-Wei LIN - Westborough MA, US
Vladimir ZLATKOVIC - Belmont MA, US
Shefali WALIA - Boxborough MA, US
Youssef Mamdouh EL-TOUKHY - Cairo, EG
Abdelrahman Alaa GOUDA - Cairo, EG
Alexander A. ALEXEYEV - Beverly MA, US
International Classification:
H03K 5/156
G06F 1/04
G06F 1/04
Abstract:
Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.