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Vladimir I Prodanov

from San Luis Obispo, CA
Age ~55
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Also known as:
Vladimir L Prodanov, Bladimir Prodanov, Vlad L Prodanov
Phone and address:
1311 Alder St, San Luis Obispo, CA 93401
(805) 439-1261
Related to:
Kosta A Prodanov, 43Katherina Prodanov, 28Evelina B Prodanov, 56
Connected to:
Aleksandar S Prodanovic, 67Branko N Prodanovic, 57Milan Prodanovic, 65Peter J Prodanov, 51Sinisa Prodanovic, 43Zoran Prodanovic, 55Ravi Prodduturi, 75Shilpa Proddutur, 48Kristen Prodehl, 29Matthew C Prodehl, 41

Vladimir Prodanov Phones & Addresses

  • 1311 Alder St, Sn Luis Obisp, CA 93401 (805) 439-1261
  • 1720 Lee Ann Ct, Sn Luis Obisp, CA 93401 (805) 439-1261
  • San Luis Obispo, CA
  • 1124 Hawthorne Dr, New Providence, NJ 07974 (908) 898-0318
  • 124 Hawthorne Dr, New Providence, NJ 07974 (908) 898-0318
  • Stonybrook, NY
  • Watchung, NJ
  • New Providnce, NJ

Resumes

Resumes

Vladimir Prodanov Photo 1

Assistant Professor, Cal Poly, Slo

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Position:
Assistant Professor at CSU, San Luis Obispo
Location:
San Luis Obispo, California Area
Industry:
Design
Work:
CSU, San Luis Obispo since Jan 2009
Assistant Professor
MHI Consulting, LLC Oct 2004 - Dec 2008
member
Agere Systems Jan 2001 - Oct 2004
MTS / SMTS
Bell Labs 1997 - 2001
MTS
Education:
State University of New York at Stony Brook 1992 - 1997
Master of Science (MS), Electrical Engineering State University of New York at Stony Brook 1992 - 1997
Doctor of Philosophy (Ph.D.), Electrical Engineering
Skills:
IC
Circuit Design
Analog
RF
VLSI
Vladimir Prodanov Photo 2

Assistant Professor At Csu, San Luis Obispo

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Location:
San Luis Obispo, California Area
Industry:
Design
Experience:
CSU, San Luis Obispo (Design industry): Assistant Professor,  (January 2009-Present) Teach Circuits and Circuit Design (mostly analog and RF)MHI Consulting, LLC (Design industry): member,  (October 2004-December 2008) consulting, SBIR grands, circuit des...

Publications

Us Patents

Method And Apparatus For Modulating Digital Data

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US Patent:
6560296, May 6, 2003
Filed:
May 4, 1999
Appl. No.:
09/304639
Inventors:
Jack Glas - Basking Ridge NJ
Vladimir Prodanov - New Providence NJ
Maurice Tarsia - Colonia NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H04L 2720
US Classification:
375308, 375261, 375279, 375298
Abstract:
The modulator includes an oscillator generating signals, each having a different phase, and a selector receiving digital data. When the digital data received by the selector changes logic state, the selector supplies a first and second plurality of signals generated by the oscillator to first and second non-linear amplifiers, respectively. An adder then adds the output of each amplifier to generate a radio frequency output.

Cmos Transconductor With Increased Dynamic Range

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US Patent:
6577170, Jun 10, 2003
Filed:
Nov 27, 2001
Appl. No.:
09/994541
Inventors:
Vladimir I. Prodanov - New Providence NJ, 07974
International Classification:
H03K 522
US Classification:
327103, 327 65, 327 77, 327563, 330253
Abstract:
A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.

Apparatus, Method And System For Common-Mode Stabilization In Circuits Having Differential Operation

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US Patent:
6580324, Jun 17, 2003
Filed:
Sep 12, 2001
Appl. No.:
09/951291
Inventors:
George Palaskas - New York NY
Vladimir I. Prodanov - New Providence NJ
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H03F 345
US Classification:
330258, 330259
Abstract:
A system, method and apparatus are disclosed for common-mode voltage feedback. The preferred system includes a plurality of differential circuits, a corresponding plurality of common-mode voltage detectors, a corresponding plurality of buffer circuits, and a common-mode control circuit. Each differential circuit is operative to produce a first differential output voltage and a second differential output voltage. Each corresponding common-mode voltage detector is operative to provide a common-mode voltage from the first differential output voltage and the second differential output voltage. The common-mode control circuit provides a control voltage signal from the common-mode voltage and from a reference voltage. Each buffer circuit is operative to adjust the corresponding common-mode voltage using the control voltage signal to provide a common-mode feedback voltage signal to the corresponding differential circuit.

Buffer Interface Architecture

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US Patent:
6693469, Feb 17, 2004
Filed:
Apr 23, 2002
Appl. No.:
10/128140
Inventors:
Vladimir I. Prodanov - New Providence NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03K 300
US Classification:
327108, 327112, 327170, 326 56, 326 58
Abstract:
An up to 3Ã breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver.

System And Method For Differential Data Detection

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US Patent:
6904538, Jun 7, 2005
Filed:
Nov 20, 2001
Appl. No.:
09/989272
Inventors:
Jack P. Glas - Basking Ridge NJ, US
Vladimir I. Prodanov - New Providence NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B001/04
US Classification:
713401, 4551142, 455110, 4551151, 375298
Abstract:
The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.

System And Method For An If-Sampling Transceiver

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US Patent:
7020221, Mar 28, 2006
Filed:
Nov 20, 2001
Appl. No.:
09/989605
Inventors:
Jack P. Glas - Basking Ridge NJ, US
Vladimir I. Prodanov - New Providence NJ, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H03H 17/30
US Classification:
375329, 375316
Abstract:
The present invention is directed toward a radio, and method for receiving radio frequency signals. The radio comprises an input signal at a first intermediate frequency, an intermediate sampling architecture, a quantizer and a baseband converter. The intermediate frequency sampling architecture comprises receiving the input signal, passing the first intermediate frequency signal through a first filter characterized by steep selectivity and narrow bandpass, converting the filtered signal to a second intermediate frequency and passing the second intermediate frequency signal through a second filter having a bandpass characteristic, but without the steep selectivity characterizing the first filter. The radio further comprises a third filter following the baseband conversion which filters out adjacent channel harmonics to obtain a wanted data signal.

Polyphase Filter With Low-Pass Response

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US Patent:
7031690, Apr 18, 2006
Filed:
Nov 14, 2002
Appl. No.:
10/294411
Inventors:
Vladimir Prodanov - New Providence NJ, US
Peter Kiss - Morristown NJ, US
Mihai Banu - New Providence NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B 1/00
US Classification:
455338, 455307, 330107
Abstract:
A complex low-pass filter that reduces the influence of component mismatch. The filter includes a first filter section for effecting a first single pole transfer function and a second filter section for effecting a second single pole transfer function, where the first and the second single pole transfer functions collectively define a conjugate pair of poles. In higher order low-pass filters, an optimal cascade order follows a shoestring pattern.

Automatic Biasing Of A Power Device For Linear Operation

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US Patent:
7084705, Aug 1, 2006
Filed:
Jun 1, 2004
Appl. No.:
10/856993
Inventors:
Vladimir Prodanov - New Providence NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03G 3/10
US Classification:
330285
Abstract:
A power device(s) is biased and operates in Class-AB. Crossover distortion is minimized over a broad range of operating conditions, not only for a nominal case. The bias current of a power transistor is automatically adjusted in response to process and temperature variations. Preferably, the adjustment is performed using an error-feedback arrangement. An exemplary ‘rule’ for bias adjustment involves satisfying a proportionality relationship between the small-signal device transconductance at the operating point, and a maximum device transconductance. A dual replica master-slave control architecture is utilized. A self-adapting circuit is provided to change the bias current (or voltage) so that the value is always the optimum value, irrespective of operating temperature and/or process variations. Self-biasing is introduced wherein no manual adjustment is necessary. A stable amplifier is formed having great robustness to process and temperature variations.
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Vladimir I Prodanov from San Luis Obispo, CA, age ~55 Get Report