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Vladan Andrijanic

from San Diego, CA
Age ~55
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Related to:
N TomcaNela Tomca, 54
Connected to:
Andrius Andrijauskas, 42Denise F Andrikowich, 64Elias Andrikopoulos, 70Melissa E Andriks, 74Christopher J Andrin, 53Carol J Andringa, 70Hans J Andringa, 78Mark W Andring, 63Thomas Andrinette, 38Jennifer M Andrino, 28

Vladan Andrijanic Phones & Addresses

  • San Diego, CA

Work

Company: Amd Oct 2002 to Jan 2009 Position: Member of technical staff - asic

Education

School / High School: University of Belgrade 1988 to 1997

Industries

Wireless

Resumes

Resumes

Vladan Andrijanic Photo 1

Principal

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Location:
San Diego, CA
Industry:
Wireless
Work:
Amd Oct 2002 - Jan 2009
Member of Technical Staff - Asic
Qualcomm Oct 2002 - Jan 2009
Principal
Hdl Design House 2000 - 2002
Senior Asic Designer
Institute Mihailo Pupin Apr 1998 - Apr 2000
Fpga and Dsp Engineer
Education:
University of Belgrade 1988 - 1997

Publications

Us Patents

Video Processing Architecture

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US Patent:
20120114045, May 10, 2012
Filed:
Nov 10, 2010
Appl. No.:
12/943446
Inventors:
CHIA-YUAN TENG - San Diego CA, US
Dan M. Chuang - San Diego CA, US
Dane Gokce - San Diego CA, US
Raghavendra C. Nagaraj - San Diego CA, US
Vladan Andrijanic - San Diego CA, US
Yiu-Wing Leung - Ontario, CA
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H04N 7/26
US Classification:
37524024, 375E07026
Abstract:
A method for video processing may include receiving video data units, and compressing the video data units to generate compressed video data units that have a variable size. The method may also include storing the compressed video data units contiguously in a memory in memory segments that have a fixed size, where the size of at least one of the compressed video data units is indivisible by the fixed size of the memory segments, and where a portion of the indivisible compressed video data unit is stored with a portion of another compressed video data unit in one of the memory segments. The method may also include determining data storage information associated with the compressed video data units, and storing the data storage information in the memory. A system may have a video processing architecture designed to support the method.

Sub-Block Level Parallel Video Coding

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US Patent:
20130188701, Jul 25, 2013
Filed:
Jan 17, 2013
Appl. No.:
13/744128
Inventors:
Shu Xiao - San Diego CA, US
Kai Wang - San Diego CA, US
Vladan Andrijanic - San Diego CA, US
Xianglin Wang - San Diego CA, US
Wei-Jung Chien - San Diego CA, US
Marta Karczewicz - San Diego CA, US
Vadim Seregin - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04N 7/26
US Classification:
37524012
Abstract:
The techniques of this disclosure are generally related to parallel coding of video units that reside along rows or columns of blocks in largest coding units. For example, the techniques include removing intra-prediction dependencies between two video units in different rows or columns to allow for parallel coding of rows or columns of the video units.

Temporal And Spatial Video Block Reordering In A Decoder To Improve Cache Hits

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US Patent:
20110150085, Jun 23, 2011
Filed:
Dec 21, 2009
Appl. No.:
12/643523
Inventors:
Vladan Andrijanic - San Diego CA, US
Serag GadelRab - Markham, CA
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H04N 7/32
US Classification:
37524012, 375E07243
Abstract:
This disclosure describes techniques in which the decoding order of video blocks is modified relative to the display order of video blocks. The decoding order may be modified temporally such that video blocks of different video frames (or other coded units) are decoded in an alternating manner. In this case, the decoding order of video blocks may alternate between video blocks of two or more different frames. Furthermore, the decoding order may also be modified spatially within a given video block such that the video blocks are decoded in an order that does not correspond to the raster scan order of the video blocks. The techniques may improve the use of memory by improving the likelihood of cache hits, thereby reducing the number of memory loads from an external memory to an internal cache associated with the decoder.

Intra Block Copy Scratch Frame Buffer

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US Patent:
20220256167, Aug 11, 2022
Filed:
Feb 11, 2021
Appl. No.:
17/173961
Inventors:
- San Diego CA, US
Gaurav Patil - San Jose CA, US
Yasutomo Matsuba - San Diego CA, US
Vladan Andrijanic - San Diego CA, US
Prasanth Gomatam - San Diego CA, US
Rajesh Chowdary Chitturi - San Diego CA, US
International Classification:
H04N 19/146
H04N 19/132
H04N 19/159
H04N 19/176
Abstract:
An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.

Intra Block Copy Scratch Frame Buffer

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US Patent:
20230059060, Feb 23, 2023
Filed:
Oct 20, 2022
Appl. No.:
18/048120
Inventors:
- San Diego CA, US
Gaurav Avinash Patil - San Jose CA, US
Yasutomo Matsuba - San Diego CA, US
Vladan Andrijanic - San Diego CA, US
Prasanth Gomatam - San Diego CA, US
Rajesh Chowdary Chitturi - San Jose CA, US
International Classification:
H04N 19/146
H04N 19/132
H04N 19/159
H04N 19/176
Abstract:
An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.

Tile-Based Processing For Video Coding

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US Patent:
20180278948, Sep 27, 2018
Filed:
Mar 23, 2017
Appl. No.:
15/467841
Inventors:
- San Diego CA, US
Hariharan Ganesh Lalgudi - San Diego CA, US
Yunqing Chen - Campbell CA, US
Vladan Andrijanic - San Diego CA, US
Shyamprasad Chikkerur - San Diego CA, US
Harikrishna Reddy - San Jose CA, US
Kai Wang - San Diego CA, US
International Classification:
H04N 19/513
H04N 19/15
H04N 19/159
H04N 19/436
H04N 19/91
H04N 19/124
Abstract:
Example video encoding techniques are described. A video encoder may generate residual data for macroblocks for tiles of a current frame. Each tile includes a plurality of macroblocks, each tile is independently encoded from the other tiles of the current frame, and a width of each tile is less than a width of the current frame. The video encoder may store the residual data in buffers. Each buffer is associated with one or more tiles, and each buffer is configured to store residual data for macroblocks for the one or more tiles with which each buffer is associated. The video encoder may read the residual data from the plurality of buffers for macroblocks of an entire row of the current frame before reading residual data from the plurality of buffers for macroblocks of any other row of the current frame, and encode values based on the read residual data.

System And Method For Multi-Tile Data Transactions In A System On A Chip

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US Patent:
20170228252, Aug 10, 2017
Filed:
Jan 13, 2017
Appl. No.:
15/406516
Inventors:
- SAN DIEGO CA, US
MEGHAL VARIA - BRAMPTON, CA
WISNU WURJANTARA - MARKHAM, CA
CLARA KA WAH SUNG - MARKHAM, CA
MARK STERNBERG - TORONTO, CA
VLADAN ANDRIJANIC - SAN DIEGO CA, US
ANTONIO RINALDI - MAPLE, CA
VINOD CHAMARTY - SAN DIEGO CA, US
POOJA SINHA - MARKHAM, CA
TAO WANG - SUNNYVALE CA, US
ANDREW GRUBER - ARLINGTON CA, US
International Classification:
G06F 9/46
G06F 17/30
G06F 15/78
Abstract:
Various embodiments of methods and systems for managing compressed data transaction sizes in a system on a chip (“SoC”) in a portable computing device (“PCD”) are disclosed. Based on lengths of compressed data tiles associated in a group, wherein the compressed data tiles are comprised within a compressed image file, multiple compressed data tiles may be aggregated into a single, multi-tile transaction. A metadata file may be generated in association with the single multi-tile transaction to identify the transaction as a multi-tile transaction and provide offset data to distinguish data associated with the compressed data tiles. Using the metadata, embodiments of the solution may provide for random access and modification of the compressed data stored in association with a multi-tile transaction.
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Vladan Andrijanic from San Diego, CA, age ~55 Get Report