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Vito Dai

from Cupertino, CA
Age ~47
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Also known as:
Vito Wang, Vito Lai
Phone and address:
8152 Park Villa Cir, Cupertino, CA 95014
Related to:
Alex Y Wang, 31Andrew Wang, 28Chia Dai, 29Qing A Li, 42Lily X Wang, 65Wei W Wang, 64Yinghwa Wang Dai, 76Min Lai, 46Yinghwa Wang, 76Zhihe Li, 69Xiaoyi Tang, 47Biao WangWei Dai, 34
Connected to:
Ai Q Dai, 61Andrea Dai, 27Anthony J Dai, 44Bei Dai, 64Cally X Dai, 32Chenkai Dai, 48Eileen Dai, 28Gonghe Dai, 67Ha T Dai, 57Haibin Dai, 49

Vito Dai Phones & Addresses

  • 8152 Park Villa Cir, Cupertino, CA 95014
  • 1907 Magdalena Cir, Santa Clara, CA 95051 (408) 557-8694
  • Sunnyvale, CA
  • 1010 Verdemar Dr, Alameda, CA 94502 (510) 748-9291
  • 1100 Pacific Marina, Alameda, CA 94501 (510) 748-9291
  • 300 Murchison Dr, Millbrae, CA 94030 (650) 697-5509
  • Pasadena, CA
  • Monterey Park, CA

Work

Company: Globalfoundries 2009 to 2015 Position: Pmts dfm cad engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Berkeley 2008 to 2008 Specialities: Electrical Engineering, Electrical Engineering and Computer Science, Computer Science, Philosophy

Skills

Semiconductors • Process Integration • Cmos • Lithography • Ic • Tcl • Semiconductor Industry • Vlsi • Photolithography • Design of Experiments • Thin Films • Failure Analysis • Product Engineering • Yield

Languages

English • Italian

Interests

Cooking • Electronics • Investing • Home Improvement • Reading • Crafts • Gourmet Cooking • Home Decoration

Industries

Semiconductors

Resumes

Resumes

Vito Dai Photo 1

Director Of Engineering

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Location:
8060 Park Villa Cir, Cupertino, CA 95014
Industry:
Semiconductors
Work:
Globalfoundries 2009 - 2015
Pmts Dfm Cad Engineer
Motivo Engineering 2009 - 2015
Director of Engineering
Amd 2005 - 2009
Senior Process Engineer
Education:
University of California, Berkeley 2008 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science, Philosophy University of California, Berkeley 2000 - 2000
Masters, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science Caltech 1998 - 1998
Bachelors, Electrical Engineering
Skills:
Semiconductors
Process Integration
Cmos
Lithography
Ic
Tcl
Semiconductor Industry
Vlsi
Photolithography
Design of Experiments
Thin Films
Failure Analysis
Product Engineering
Yield
Interests:
Cooking
Electronics
Investing
Home Improvement
Reading
Crafts
Gourmet Cooking
Home Decoration
Languages:
English
Italian

Publications

Us Patents

Methods For Pattern Matching In A Double Patterning Technology-Compliant Physical Design Flow

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US Patent:
8418105, Apr 9, 2013
Filed:
Jan 12, 2012
Appl. No.:
13/349412
Inventors:
Lynn T. Wang - Fremont CA, US
Vito Dai - Santa Clara CA, US
Luigi Capodieci - Santa Cruz CA, US
Assignee:
Globalfoundries, Inc. - Grand Cayman
International Classification:
G06F 17/50
US Classification:
716110
Abstract:
A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.

Method And Apparatus For Pattern Adjusted Timing Via Pattern Matching

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US Patent:
8453089, May 28, 2013
Filed:
Oct 3, 2011
Appl. No.:
13/251437
Inventors:
Kah Ching Edward Teoh - Singapore, SG
Vito Dai - Santa Clara CA, US
Assignee:
Globalfoundries Singapore Pte. Ltd. - Singapore
International Classification:
G06F 17/50
US Classification:
716113, 716111, 716112, 716115, 716132, 716139, 716 55
Abstract:
An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.

Methods For Decomposing Circuit Design Layouts And For Fabricating Semiconductor Devices Using Decomposed Patterns

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US Patent:
8555215, Oct 8, 2013
Filed:
Feb 20, 2012
Appl. No.:
13/400445
Inventors:
Yi Zou - Foster City CA, US
Swamy Maddu - Sunnyvale CA, US
Lynn T. Wang - Fremont CA, US
Vito Dai - Santa Clara CA, US
Luigi Capodieci - Santa Cruz CA, US
Peng Xie - Rochester NY, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
G06F 17/50
US Classification:
716 55, 716 50, 716 51, 716 52, 716 53, 716 54, 716124, 716125, 716139
Abstract:
Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Design Rules Checking Augmented With Pattern Matching

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US Patent:
20080148211, Jun 19, 2008
Filed:
Dec 19, 2006
Appl. No.:
11/613006
Inventors:
Vito Dai - Santa Clara CA, US
Jie Yang - Sunnyvale CA, US
Norma Rodriguez - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G06F 9/455
US Classification:
716 11
Abstract:
Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.

Pattern Matching For Predicting Defect Limited Yield

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US Patent:
20150286763, Oct 8, 2015
Filed:
Apr 2, 2014
Appl. No.:
14/243551
Inventors:
- Grand Cayman, KY
Sriram MADHAVAN - Santa Clara CA, US
Vito DAI - Santa Clara CA, US
Luigi CAPODIECI - Santa Cruz CA, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
G06F 17/50
Abstract:
Methods and apparatuses for pattern-based methodology for CAA and defect limited yield analysis are disclosed. Embodiments may include matching one or more patterns within a layer of an integrated circuit design layout to one or more pre-characterized patterns within a pattern library, determining respective critical areas of the one or more patterns based on respective pre-characterized critical areas of the one or more pre-characterized patterns, and predicting a defect limited yield of the layer based on the respective pre-characterized critical areas.

Methods For Fabricating Integrated Circuits Including Generating E-Beam Patterns For Directed Self-Assembly

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US Patent:
20150126032, May 7, 2015
Filed:
Nov 5, 2013
Appl. No.:
14/072164
Inventors:
- Grand Cayman, KY
Yi Zou - Foster City CA, US
Vito Dai - Santa Clara CA, US
Assignee:
GLOBAL FOUNDRIES, Inc. - Grand Cayman
International Classification:
G06F 17/50
H01L 21/033
H01L 21/027
US Classification:
438694, 716 55
Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.

Methods For Fabricating Integrated Circuits Including Generating Photomasks For Directed Self-Assembly

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US Patent:
20150012896, Jan 8, 2015
Filed:
Jul 8, 2013
Appl. No.:
13/936910
Inventors:
- Grand Cayman, KY
Yi Zou - Foster City CA, US
Vito Dai - Santa Clara CA, US
International Classification:
G03F 7/20
US Classification:
716 55
Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.

Methods For Fabricating Integrated Circuits Including Generating Photomasks For Directed Self-Assembly

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US Patent:
20150012897, Jan 8, 2015
Filed:
Jul 8, 2013
Appl. No.:
13/936924
Inventors:
- Grand Cayman, KY
Yi Zou - Foster City CA, US
Vito Dai - Santa Clara CA, US
International Classification:
G03F 7/20
US Classification:
716 55
Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.
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Vito Dai from Cupertino, CA, age ~47 Get Report