Vipul V Parikh

7146303, Dec 5, 2006

Feb 28, 2003

10/376753

Aninda Roy - San Jose CA, US
Vipul Parikh - Union City CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

703 18, 716 11, 716 17

A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.

7293157, Nov 6, 2007

Nov 24, 2004

10/997394

Vipul Y. Parikh - Union City CA, US
Quinn A. Jacobson - Sunnyvale CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 12/08

711207, 711206, 711216, 711209, 711147, 711153

One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.

6553477, Apr 22, 2003

Nov 6, 2000

09/707347

Murali V. Krishna - Campbell CA
Vipul Parikh - Campbell CA
Michael Butler - Campbell CA
Gene Shen - Campbell CA
Masahito Kubo - Kawasaki, JP

Fujitsu Limited - Kawasaki

G06F 1200

711207, 711122, 711126, 711128, 711205, 711206, 700200

A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.