US Patent:
20020019202, Feb 14, 2002
Inventors:
Terence Thomas - Newark DE, US
Qianqiu (Christine) Ye - Wilmington DE, US
Joseph So - Newark DE, US
Peter Burke - Vancouver WA, US
Vikas Sachan - Richardson TX, US
Elizabeth Langlois - Wilimington DE, US
Keith Pierce - Colorado Springs CO, US
Craig Lack - Wilmington DE, US
David Gettman - Fresno CA, US
Hiroyuki Senoo - Kohriyama-Shi, JP
Kouchi Yoshida - Yamato Kohriyama-Shi, JP
Yoshikazu Nishida - Yamato Kohriyama-shi, JP
Vilas Koinkar - Wilmington DE, US
Raymond Lavoie - Chesapeake City MD, US
International Classification:
B24B007/22
Abstract:
A two-step method for chemical mechanical polishing of a semiconductor substrate having successive layers, comprised of, a metal layer, an underlying barrier film and an underlying dielectric layer. The first polishing step is performed utilizing a slurry composition selective to the metal in the metal layer, to remove the metal at a high removal rate during polishing, and the second polishing step is performed utilizing a slurry composition selective to the barrier film and least selective to the metal layer and the underlying dielectric layer. In an alternate embodiment, the second polishing step is performed with a slurry equally selective to the barrier layer and the underlying dielectric layer and least selective to the metal of the metal layer, to remove the barrier layer at a high removal rate during polishing, and level a surface of the dielectric layer to the surface of the metal interconnection structure in the underlying dielectric layer.