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Vidmantas V Sargunas

from Rio Rancho, NM
Age ~62
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Also known as:
Vidas Vaiva Sargunas, Vaiva Sargunas, Sargunas Vidmantas, Vidmantas S
Related to:
Paul SargunasVaiva Sargunas, 61
Connected to:
Christopher Sargunam, 46Saloomeh Sarhadi, 69Amira A Sarhan, 81Eman K Sarhan, 54Frank Sarhan, 57Hanan Sarhan, 59Mahmoud H Sarhan, 65Nabil J Sarhan, 52Sami Sarhan, 51Sara A Sarhan, 71

Vidmantas Sargunas Phones & Addresses

  • Rio Rancho, NM
  • Cave Creek, AZ
  • Clifton Park, NY
  • Fishkill, NY
  • Phoenix, AZ
  • Maricopa, AZ
  • 15 Chatsworth Way, Clifton Park, NY 12065

Work

Company: Stmicroelectronics Jan 1996 Position: Process engineering section manager

Education

Degree: Lean six sigma black belt School / High School: Villanova University 2010 to 2010

Industries

Semiconductors

Resumes

Resumes

Vidmantas Sargunas Photo 1

Experienced Semiconductor Professional, Cssbb, Phd(Physics)

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Position:
Process Engineering Section manager at STMicroelectronics
Location:
Phoenix, Arizona Area
Industry:
Semiconductors
Work:
STMicroelectronics since Jan 1996
Process Engineering Section manager
McMaster University 1991 - 1995
visiting scientist
Kaunas Radio Measurement Institute 1989 - 1990
Engineer (part time)
Education:
Villanova University 2010 - 2010
Lean six sigma black belt Kaunas University of Technology/Vilnius University 1987 - 1991
Dr.Sc., Physics of semiconductors and dielectrics Moscow Engineering Physics Institute 1983 - 1986
M.Sc., Engineering Physics (solid state physics and quantum electronics) Kaunas University of Technology 1980 - 1983
B.Sc., EE

Publications

Us Patents

Integrated Circuits Having Finfets With Improved Doped Channel Regions And Methods For Fabricating Same

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US Patent:
20150035062, Feb 5, 2015
Filed:
Jul 30, 2013
Appl. No.:
13/954289
Inventors:
- GRAND CAYMAN, KY
Bharat KRISHNAN - Clifton Park NY, US
Bongki LEE - Malta NY, US
Vidmantas SARGUNAS - Clifton Park NY, US
Weihua TONG - Mechanicville NY, US
Seung KIM - Mechanicville NY, US
Assignee:
GLOBALFOUNDRIES, INC. - GRAND CAYMAN
International Classification:
H01L 29/66
H01L 21/8238
H01L 29/78
US Classification:
257368, 438283, 438199
Abstract:
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Methods Of Forming Metal Silicide Regions On Semiconductor Devices Using Millisecond Annealing Techniques

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US Patent:
20140363972, Dec 11, 2014
Filed:
Jun 5, 2013
Appl. No.:
13/910430
Inventors:
- Grand Cayman KY, US
Vidmantas Sargunas - Clifton Park NY, US
International Classification:
H01L 21/285
US Classification:
438683
Abstract:
In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
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Vidmantas V Sargunas from Rio Rancho, NM, age ~62 Get Report