Venkatraman E Iyer

6359951, Mar 19, 2002

Jun 3, 1998

09/089923

Jeffrey C. Morriss - Cornelius OR
Venkatraman Iyer - Portland OR

Intel Corporation - Santa Clara CA

H01L 2300

375377, 370522, 326 86

Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

6744810, Jun 1, 2004

Dec 10, 1999

09/459744

Venkatraman Iyer - Beaverton OR
John Todd West - Seattle WA

Intel Corporation - Santa Clara CA

G06F 15167

375214, 375257, 709213

A signal repeater for use between a serial data line and a peripheral device is disclosed. The signal repeater receives bus signals on the serial data line at a first voltage and translates the bus signal into a device signal of a second voltage. Also, the signal repeater is operative to receives device signals from the device at the second voltage and translates the device signal into a bus signal at the first voltage.

20100330927, Dec 30, 2010

Jun 30, 2009

12/495706

Naveen Cherukuri - San Jose CA, US
Jeffrey Wilcox - Boulder Creek CA, US
Venkatraman Iyer - Portland OR, US
Selim Bilgin - Hillsboro OR, US
David D. Dunning - Portland OR, US
Robin Tim Frodsham - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US
Sanjay Dabral - Palo Alto CA, US

H04B 7/00

455 68, 455522

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

20120079160, Mar 29, 2012

Sep 24, 2010

12/890252

VENKATRAMAN IYER - Austin TX, US
Arvind Kumar - Brookline MA, US
Santanu Chaudhuri - Mountain View CA, US
Darren S. Jue - Sunnyvale CA, US
Dennis R. Halicki - Hillsboro OR, US

G06F 13/36

710311

A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.

20130007491, Jan 3, 2013

Jul 1, 2011

13/175794

VENKATRAMAN IYER - Austin TX, US
ROBERT G. BLANKENSHIP - Tacoma WA, US
DENNIS R. HALICKI - Hillsboro OR, US

G06F 1/32

713321

Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed.

20130007502, Jan 3, 2013

Jul 1, 2011

13/175798

VENKATRAMAN IYER - Austin TX, US
ROBERT G. BLANKENSHIP - Tacoma WA, US
ALLEN J. BAUM - Palo Alto CA, US

G06F 11/20

714 3, 714E11071

Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

20130279622, Oct 24, 2013

Sep 30, 2011

13/976680

Venkatraman Iyer - Austin TX, US
Santanu Chaudhuri - Mountain View CA, US
Stephen S. Chang - Portland OR, US

H04L 1/00

375285

A method and system to reduce the power supply noise of a platform during the training of high speed communication links. In one embodiment of the invention, the device has logic to stagger a bit lock pattern for each of one or more communication links and scramble a training sequence for each of the one or more communication links. By doing so, it removes the need for anti-noise circuits and in turn, reduces the silicon area and power of the devices. Further, by having the logic in the physical layers to facilitate the training of the communication links, it eliminates the need to redesign the package of the devices to shift the resonant frequencies.

20140002102, Jan 2, 2014

Dec 28, 2012

13/729756

Thanunathan Rangarajan - Bangalore, IN
Shreesh Chhabbi - Bangalore, IN
Arvind A. Kumar - Beaverton OR, US
Venkatraman Iyer - Austin TX, US

G01R 31/04

324538

Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.