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Venkataramanan M Balakrishnan

from Lyndhurst, OH
Age ~61
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Also known as:
Venkataraman M Balakrishnan, Balakrishnan V Venkataramanan, Venkataremanan Balakrishnan, Venkatareman Balakrishnan, Venkataramanan Balakrish, Catherine Lee
Related to:
Venkataraman Balakrishnan, 61
Connected to:
Anand S Balakrishnan, 45Annapurna Balakrishnan, 63Arjun Balakrishnan, 57Baiju Balakrishnan, 41Dilip Balakrishnan, 54Gokul Balakrishnan, 40Govind Balakrishnan, 64Jeyendran Balakrishnan, 58Kannan Balakrishnan, 57Karthik Balakrishnan, 54

Venkataramanan Balakrishnan Phones & Addresses

  • Lyndhurst, OH
  • West Lafayette, IN

Resumes

Resumes

Venkataramanan Balakrishnan Photo 1

Charles H Phipps Dean Of Engineering And Professor Of Eecs Case School Of Engineering, Case Western Reserve

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Location:
5027 Bristol Ct, Lyndhurst, OH 44124
Industry:
Higher Education
Work:
Case Western Reserve University
Charles H Phipps Dean of Engineering and Professor of Eecs Case School of Engineering, Case Western Reserve
Purdue University
Professor and Head of Electrical and Computer Engineering
Education:
Stanford University 1985 - 1992
Doctorates, Doctor of Philosophy, Philosophy
Skills:
Computer Engineering
Venkataramanan Balakrishnan Photo 2

Senior Consultant

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Location:
Cleveland, OH
Work:

Senior Consultant
Venkataramanan Balakrishnan Photo 3

Senior Consultant In Infosys Ltd

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Location:
Cleveland, OH
Work:
Infosys
Senior Consultant In Infosys Ltd
Infosys Aug 2011 - Jun 2012
Consultant
Temenos Feb 2011 - Aug 2011
Business Analyst
Icici Bank Sep 2003 - Feb 2011
Officer To Unit Manager
Education:
Symbiosis Institute of Management Studies 2004 - 2006
D.g.vaishnava College 2000 - 2003
Bachelor of Commerce, Bachelors, Business Management, Accounting Ramana Vidya Kendra Matric Hr Sec School 1998 - 2000
Skills:
Microsoft Office
Microsoft Excel
Microsoft Word
Customer Service
Banking
Consulting
Finance
Core Banking
Interests:
Playing Chess
Watching Cricket

Publications

Wikipedia References

Venkataramanan Balakrishnan Photo 4

Venkataramanan Balakrishnan

Us Patents

Computationally Efficient Modeling And Simulation Of Large Scale Systems

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US Patent:
8336014, Dec 18, 2012
Filed:
Aug 9, 2010
Appl. No.:
12/852942
Inventors:
Jitesh Jain - Rajasthan, IN
Stephen F. Cauley - West Lafayette IN, US
Hong Li - He nan, CN
Venkataramanan Balakrishnan - West Lafayette IN, US
Assignee:
Purdue Research Foundation - West Lafayette IN
International Classification:
G06F 17/50
US Classification:
716115, 716106, 716111, 703 2, 703 14
Abstract:
A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix Xand at least one other matrix, with first equation including XY, XA, and XP, and the second equation including XA and XP.

Computationally Efficient Modeling And Simulation Of Large Scale Systems

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US Patent:
20130124168, May 16, 2013
Filed:
Dec 10, 2012
Appl. No.:
13/710145
Inventors:
Purdue Research Foundation - West Lafayette IN, US
Stephen F. Cauley - West Lafayette IN, US
Hong Li - Xin Xiang, CN
Venkataramanan Balakrishnan - West Lafayette IN, US
Assignee:
Purdue Research Foundation - West Lafayette IN
International Classification:
G06F 17/50
US Classification:
703 2
Abstract:
A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Computationally Efficient Modeling And Simulation Of Large Scale Systems

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US Patent:
7774725, Aug 10, 2010
Filed:
Nov 6, 2006
Appl. No.:
11/593465
Inventors:
Jitesh Jain - Rajasthan, IN
Stephen F. Cauley - West Lafayette IN, US
Hong Li - He nan, CN
Venkataramanan Balakrishnan - West Lafayette IN, US
Assignee:
Purdue Research Foundation - West Lafayette IN
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6, 703 2, 703 14
Abstract:
A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix Xand at least one other matrix, with first equation including XY, XA, and XP, and the second equation including XA and XP.
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Venkataramanan M Balakrishnan from Lyndhurst, OH, age ~61 Get Report