Resumes
Resumes
Venkata Griddalur Phones & Addresses
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1357 Whispering Oaks Way, Pleasanton, CA 94566
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Reno, NV
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Pioneer, CA
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Fremont, CA
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Concord, CA
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Berkeley, CA
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San Jose, CA
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Mountain View, CA
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Sunnyvale, CA
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Alameda, CA
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166 Paso Olmo Ter, Fremont, CA 94539
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
Mission Ridge Owners' Association
2000 Crow Cyn Pl, San Ramon, CA 94583
Principal
Crania Tech
Business Services at Non-Commercial Site
Business Services at Non-Commercial Site
4784 Lago Vis Cir, San Jose, CA 95129
President
CRANIATECH, INC
166 Paso Olmo Ter, Fremont, CA 94539
4515 Carlyle Ct, Santa Clara, CA 95054
4784 Lago Vis Cir, San Jose, CA 95129
4515 Carlyle Ct, Santa Clara, CA 95054
4784 Lago Vis Cir, San Jose, CA 95129
Publications
Us Patents
Inline Clustered Defect Reduction
View pageUS Patent:
7739064, Jun 15, 2010
Filed:
May 9, 2003
Appl. No.:
10/434856
Inventors:
Gregory G. Ryker - Ben Lomond CA, US
Venkata R. Griddalur - Fremont CA, US
Venkata R. Griddalur - Fremont CA, US
Assignee:
KLA-Tencor Corporation - Milpitas CA
International Classification:
G01R 31/00
US Classification:
702 81, 702118, 702182, 700121
Abstract:
A method of reducing an inspection time required for inspecting a wafer with an automated inspection system. A target time is determined, to which the inspection time is to be reduced. A maximum number of analyses that the automated inspection system can perform during the target time is determined, and analysis of the wafer is limited to the maximum number of analyses, thereby enabling the automated inspection system to reduce the inspection time required to inspect the wafer to the target time. In this manner, the length of time required to inspect the wafer with the automated inspection system does not exceed the target time, because the number of inspections that can be performed within the target time has been determined. Thus, the inspection time for each wafer is kept to a desired level.