Resumes
Resumes
![Vatsal Dholabhai Photo 1 Vatsal Dholabhai Photo 1](/img/not-found.png)
Physical Design For Edge Inference Asics For Neural Networks, Ai And Machine Learning
View pageLocation:
Boise, ID
Industry:
Semiconductors
Work:
NVIDIA Corp since Sep 2011
Senior Physical Implementation Engineer
Synaptics Inc Jan 2011 - Sep 2011
IC Design Team Lead
Synaptics Inc Mar 2007 - Dec 2010
IC Design Engineer
Transmeta Corp Apr 2006 - Mar 2007
Senior Circuit Design Engineer
Transmeta Corp Aug 2003 - Mar 2006
Circuit Design Engineer
Senior Physical Implementation Engineer
Synaptics Inc Jan 2011 - Sep 2011
IC Design Team Lead
Synaptics Inc Mar 2007 - Dec 2010
IC Design Engineer
Transmeta Corp Apr 2006 - Mar 2007
Senior Circuit Design Engineer
Transmeta Corp Aug 2003 - Mar 2006
Circuit Design Engineer
Education:
Stanford University 2001 - 2003
National Institute of Technology Surat 1997 - 2001
National Institute of Technology Surat 1997 - 2001
Skills:
Circuit Design
Asic
Physical Design
Timing Closure
Static Timing Analysis
Application Specific Integrated Circuits
System on A Chip
Semiconductors
Integrated Circuit Design
Microprocessors
Integrated Circuits
Floorplanning
Logic Synthesis
Project Management
Feasibility Studies
Pnr
Cadence Virtuoso
Cadence Schematic Capture
Cadence Encounter
Cadence Virtuoso Layout Editor
Synopsys Primetime
Synopsys Tools
Mentor Graphics
Hspice
Spice
Verilog
Vhdl
Clock Tree Synthesis
Clocks
Clock Distribution
Schematic Capture
Formal Verification
Functional Verification
Gds
Design Rule Checking
People Management
People Development
Project Planning
Project Estimation
Analytical Skills
Cross Functional Team Leadership
Communication
Grant Writing
Negotiation
Strategy
Vendor Management
Problem Solving
Perl
Tcl
Shell Scripting
Asic
Physical Design
Timing Closure
Static Timing Analysis
Application Specific Integrated Circuits
System on A Chip
Semiconductors
Integrated Circuit Design
Microprocessors
Integrated Circuits
Floorplanning
Logic Synthesis
Project Management
Feasibility Studies
Pnr
Cadence Virtuoso
Cadence Schematic Capture
Cadence Encounter
Cadence Virtuoso Layout Editor
Synopsys Primetime
Synopsys Tools
Mentor Graphics
Hspice
Spice
Verilog
Vhdl
Clock Tree Synthesis
Clocks
Clock Distribution
Schematic Capture
Formal Verification
Functional Verification
Gds
Design Rule Checking
People Management
People Development
Project Planning
Project Estimation
Analytical Skills
Cross Functional Team Leadership
Communication
Grant Writing
Negotiation
Strategy
Vendor Management
Problem Solving
Perl
Tcl
Shell Scripting
Languages:
Gujarati
Hindi
English
Hindi
English