Resumes
Resumes
Vatsa Santhanam Phones & Addresses
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22465 Linda Ann Ct, Cupertino, CA 95014 (408) 720-8156
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2075 Anthony Dr, Campbell, CA 95008 (408) 374-8669
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Sunnyvale, CA
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Santa Clara, CA
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Milpitas, CA
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22465 Linda Ann Ct, Cupertino, CA 95014
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
Emails
Publications
Us Patents
User Controlled Relaxation Of Optimization Constraints Related To Volatile Memory References
View pageUS Patent:
6634021, Oct 14, 2003
Filed:
Apr 16, 2001
Appl. No.:
09/836667
Inventors:
Vatsa Santhanam - Campbell CA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 945
US Classification:
717151, 717153
Abstract:
A regime of keywords modifying a volatile type-qualifier for use in source code accessing volatile objects via, for example, pointers to volatile memory locations. Each keyword permits corresponding selected optimizations by a compiler even though the volatile type-qualifier is also declared. Users select and combine keywords so as to relax corresponding optimization constraints otherwise ordained by use of the volatile type-qualifier.
Programmatic Access To The Widest Mode Floating-Point Arithmetic Supported By A Processor
View pageUS Patent:
6748587, Jun 8, 2004
Filed:
Jan 2, 1998
Appl. No.:
09/002404
Inventors:
Vatsa Santhanam - Campbell CA
David Gross - Campbell CA
John Kwan - Foster City CA
David Gross - Campbell CA
John Kwan - Foster City CA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 945
US Classification:
717140
Abstract:
A software mechanism for enabling a programmer to embed selected machine instructions into program source code in a convenient fashion, and optionally restricting the re-ordering of such instructions by the compiler without making any significant modifications to the compiler processing. Using a table-driven approach, the mechanism parses the embedded machine instruction constructs and verifies syntax and semantic correctness. The mechanism then translates the constructs into low-level compiler internal representations that may be integrated into other compiler code with minimal compiler changes. When also supported by a robust underlying inter-module optimization framework, library routines containing embedded machine instructions according to the present invention can be inlined into applications. When those applications invoke such library routines, the present invention enables the routines to be optimized more effectively, thereby improving run-time application performance. A mechanism is also disclosed using a â_fpregâ data type to enable floating-point arithmetic to be programmed from a source level where the programmer gains access to the full width of the floating-point register representation of the underlying processor.
Method And Apparatus For Ordered Predicate Phi In Static Single Assignment Form
View pageUS Patent:
6898787, May 24, 2005
Filed:
Mar 22, 2001
Appl. No.:
09/814511
Inventors:
Carol Linda Thompson - San Jose CA, US
Vatsa Santhanam - Campbell CA, US
Vasanth Bala - Sudbury MA, US
Vatsa Santhanam - Campbell CA, US
Vasanth Bala - Sudbury MA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F009/45
US Classification:
717152, 717141, 717142, 717158, 717159
Abstract:
A Φ function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the Φ function indicate the condition under which the corresponding source operand is live and provide correct materialization of the Φ functions after code reordering. For control functions Φrepresenting a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The Φoperands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined.
Programmatic Access To The Widest Mode Floating-Point Arithmetic Supported By A Processor
View pageUS Patent:
7530061, May 5, 2009
Filed:
Mar 20, 2003
Appl. No.:
10/393144
Inventors:
Vatsa Santhanam - Campbell CA, US
David Gross - Campbell CA, US
John Kwan - Foster City CA, US
David Gross - Campbell CA, US
John Kwan - Foster City CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/45
US Classification:
717157, 717116, 717159
Abstract:
A software mechanism for enabling a programmer to embed selected machine instructions into program source code in a convenient fashion, and optionally restricting the re-ordering of such instructions by the compiler without making any significant modifications to the compiler processing. Using a table-driven approach, the mechanism parses the embedded machine instruction constructs and verifies syntax and semantic correctness. The mechanism then translates the constructs into low-level compiler internal representations that may be integrated into other compiler code with minimal compiler changes. When also supported by a robust underlying inter-module optimization framework, library routines containing embedded machine instructions according to the present invention can be inlined into applications. When those applications invoke such library routines, the present invention enables the routines to be optimized more effectively, thereby improving run-time application performance. A mechanism is also disclosed using a “_fpreg” data type to enable floating-point arithmetic to be programmed from a source level where the programmer gains access to the full width of the floating-point register representation of the underlying processor.
Efficient Use Of The Base Register Auto-Increment Feature Of Memory Access Instructions
View pageUS Patent:
61517054, Nov 21, 2000
Filed:
Oct 30, 1997
Appl. No.:
8/960848
Inventors:
Vatsa Santhanam - Campbell CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1204
US Classification:
717 9
Abstract:
The present invention is a compiler optimization algorithm that reduces address computation overhead for architectures that support an auto-increment addressing mode for memory access instructions. The compiler algorithm identifies opportunities for auto-increment synthesis in a low level intermediate representation. Candidate loads and stores are transformed to use a base+displacement addressing mode (even if a base+displacement addressing mode is not supported in the target architecture) prior to instruction scheduling. After instruction scheduling, the pseudo (base+displacement) instructions are transformed back into memory operations that increment their base register operands to set up effective memory addresses.
Efficient Explicit Data Prefetching Analysis And Code Generation In A Low-Level Optimizer For Inserting Prefetch Instructions Into Loops Of Applications
View pageUS Patent:
57040532, Dec 30, 1997
Filed:
May 18, 1995
Appl. No.:
8/443653
Inventors:
Vatsa Santhanam - Campbell CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 945
US Classification:
284383
Abstract:
A compiler that facilitates efficient insertion of explicit data prefetch instructions into loop structures within applications uses simple address expression analysis to determine data prefetching requirements. Analysis and explicit data cache prefetch instruction insertion are performed by the compiler in a machine-instruction level optimizer to provide access to more accurate expected loop iteration latency information. Such prefetch instruction insertion strategy tolerates worst-case alignment of user data structures relative to data cache lines. Execution profiles from previous runs of an application are exploited in the insertion of prefetch instructions into loops with internal control flow. Cache line reuse patterns across loop iterations are recognized to eliminate unnecessary prefetch instructions. The prefetch insertion algorithm is integrated with other low-level optimization phases, such as loop unrolling, register reassociation, and instruction scheduling.
Cost-Sensitive Ssa-Based Strength Reduction Algorithm For A Machine With Predication Support And Segmented Addresses
View pageUS Patent:
62861352, Sep 4, 2001
Filed:
Mar 26, 1997
Appl. No.:
8/824484
Inventors:
Vatsa Santhanam - Campbell CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 945
US Classification:
717 9
Abstract:
A compiler optimization algorithm that deals with aggressive strength reduction of integer machine instructions found in loops. The algorithm permits the strength reduction of such machine instructions whose execution may be guarded by predicate values. In addition, the algorithm allows the strength reduction of address calculations consumed by memory reference instructions accessing data in a segmented virtual address space. The algorithm also permits aggressive SSA-based strength reduction of non-address integer computations found in loops that are linear functions of loop induction variables. The algorithm incorporates profitability considerations by reducing the cost of updating strength-reduction temporaries and ensures that the strength-reduction transformation results in an overall reduction of the path-lengths within loop bodies, without creating excessive register pressure.
Method And Apparatus For Compiling Computer Programs With Interprocedural Register Allocation
View pageUS Patent:
55554172, Sep 10, 1996
Filed:
Jan 23, 1995
Appl. No.:
8/313432
Inventors:
Daryl Odnert - Boulder Creek CA
Vatsa Santhanam - Sunnyvale CA
Vatsa Santhanam - Sunnyvale CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 944
G06F 945
G06F 945
US Classification:
395700
Abstract:
Optimization techniques are implemented by means of a program analyzer used in connection with a program compiler to optimize usage of limited register resources in a computer processor. The first optimization technique, called interprocedural global variable promotion allows the global variables of a program to be accessed in common registers across a plurality of procedures. Moreover, a single common register can be used for different global variables in distinct regions of a program call graph. This is realized by identifying subgraphs, of the program call graph, called webs, where the variable is used. The second optimization technique, called spill code motion, involves the identification of regions of the call graph, called clusters, that facilitate the movement of spill instructions to procedures which are executed relatively less often. This decreases the overhead of register saves and restores which must be executed for procedure calls.