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Van Nghi Ton

from Oakland, CA
Age ~45

Van Ton Phones & Addresses

  • Oakland, CA
  • San Jose, CA
  • Milpitas, CA

Professional Records

Medicine Doctors

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Van Ton

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Resumes

Resumes

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Van Ton

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Location:
San Francisco Bay Area
Industry:
Higher Education
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Van Ton

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Van Ton

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Circuit Design Engineer At Globalfoundries

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Location:
San Francisco Bay Area
Industry:
Semiconductors
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Van Ton

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Location:
United States

Publications

Us Patents

Deposition Of Thick Bpsg Layers As Upper And Lower Cladding For Optoelectronics Applications

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US Patent:
7062141, Jun 13, 2006
Filed:
Dec 12, 2002
Appl. No.:
10/319417
Inventors:
Rong Pan - San Jose CA, US
Van Q. Ton - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
G02B 6/10
US Classification:
385129, 385131, 65386
Abstract:
Undercladding and uppercladding layers that form part of an optical waveguide are deposited with a thermal CVD technique. The optical waveguide has a structure in which optical cores are formed over the undercladding layer and in which the uppercladding layer is formed over and between the optical cores. Generally, the optical cores have a refractive index greater than a refractive index of the cladding layers. A borophosphosilicate-glass layer may be used as one or both of the cladding layers. Thick cladding layers may be formed by cyclically depositing and annealing portions of the layer.

Gap-Fill Techniques

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US Patent:
20050136684, Jun 23, 2005
Filed:
Dec 23, 2003
Appl. No.:
10/746695
Inventors:
Kevin Mukai - Santa Clara CA, US
Kimberly Branshaw - Santa Clara CA, US
Zheng Yuan - Fremont CA, US
Xinyun Xia - San Jose CA, US
Xiaolin Chen - San Jose CA, US
Dongqing Li - Santa Clara CA, US
M. Karim - San Jose CA, US
Van Ton - San Jose CA, US
Cary Ching - Sunnyvale CA, US
Nitin Ingle - Campbell CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L021/31
H01L021/469
US Classification:
438778000, 438788000
Abstract:
A variety of techniques may be employed, separately or in combination, to improve the gap-filling performance of a dielectric material formed by chemical vapor deposition (CVD). In one approach, a first dielectric layer is deposited using sub-atmospheric chemical vapor deposition (SACVD), followed by a second dielectric layer deposited by high density plasma chemical vapor deposition (HDP-CVD) or plasma-enhanced chemical vapor deposition (PECVD). In another approach, a SACVD dielectric layer is deposited in the presence of reactive ionic species flowed from a remote plasma chamber into the processing chamber, which performs etching during the deposition process. In still another approach, high aspect trenches may be filled utilizing SACVD in combination with oxide layers deposited at high temperatures.

Method And Means For Data Detection In Scsi Ultra-3 Disc Interface

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US Patent:
6621883, Sep 16, 2003
Filed:
Jan 4, 2000
Appl. No.:
09/476922
Inventors:
Van T. Ton - San Jose CA
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H04L 2300
US Classification:
375377, 713400, 327141
Abstract:
A method for data detection includes signal transition detection of an input signal. When a falling edge is detected, a rising edge in a negative signal is generated. When a rising edge is detected, a rising edge in a positive signal is generated. Data is latched from the bus for the rising edge of the positive/negative edge signal. A falling edge in the positive/negative edge signal is generated after a period of time. The steps are repeated for each detected signal transition. A data detection apparatus includes a QAEDN to generate a rising edge on the negative signal for detected falling edges. A memory unit latches data from the bus for rising edges of the negative signal. A QAEDP generates a rising edge on a positive edge signal in response to detected rising edges. A memory unit latches data from the bus for rising edges of the positive signal.
Van Nghi Ton from Oakland, CA, age ~45 Get Report