Search

Valeria M Bertacco

from Ann Arbor, MI
Age ~54
Get Report
Also known as:
Valeri M Bertacco, Baleria Bertacco
Related to:
Bruno Bertacco
Connected to:
Armand T Bertacchi, 72Gerry D Bertacchi, 68Amy M Bertacini, 42Richard A Bertacini, 91Alan J Bertagnoli, 65Andrea C Bertagna, 40Chad Bertagnoli, 54David G Bertagni, 55Jon D Bertagnolli, 60Leann M Bertagnoli, 46

Valeria Bertacco Phones & Addresses

  • Ann Arbor, MI
  • 796 Escondido Rd, Stanford, CA 94305
  • Palo Alto, CA
  • PO Box 19665, Stanford, CA 94309

Work

Company: University of michigan Sep 2003 Position: Professor

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Stanford University 1998 to 2003 Specialities: Electrical Engineering

Skills

Research • C++

Industries

Research

Resumes

Resumes

Valeria Bertacco Photo 1

Professor

View page
Location:
Detroit, MI
Industry:
Research
Work:
University of Michigan
Professor
Synopsys 1997 - 2001
Staff R and D Engineer
Education:
Stanford University 1998 - 2003
Doctorates, Doctor of Philosophy, Electrical Engineering Stanford University 1996 - 1998
Master of Science, Masters, Electrical Engineering Università Degli Studi Di Padova 1989 - 1995
Skills:
Research
C++

Publications

Us Patents

Microprocessor And Method For Detecting Faults Therein

View page
US Patent:
7966538, Jun 21, 2011
Filed:
Oct 16, 2008
Appl. No.:
12/252861
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
Smitha Shyam - San Jose CA, US
Kypros Constantinides - Ann Arbor MI, US
Sujay Phadke - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G01R 31/28
US Classification:
714736
Abstract:
A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

Microprocessor And Method For Detecting Faults Therein

View page
US Patent:
8051368, Nov 1, 2011
Filed:
Feb 28, 2011
Appl. No.:
13/036276
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
Smitha Shyam - San Jose CA, US
Kypros Constantinides - Ann Arbor MI, US
Sujay Phadke - Ann Arbor MI, US
Assignee:
The Regents of the Univeristy of Michigan - Ann Arbor MI
International Classification:
G06F 7/02
US Classification:
714819
Abstract:
A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

Microprocessor And Method For Detecting Faults Therein

View page
US Patent:
8341473, Dec 25, 2012
Filed:
Sep 23, 2011
Appl. No.:
13/242906
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
Smitha Shyam - San Jose CA, US
Kypros Constantinides - Ann Arbor MI, US
Sujay Phadke - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G01R 31/28
US Classification:
714726, 714724
Abstract:
A microprocessor has a silicon area comprising a plurality of transistors implemented on the silicon area and a fault detection circuit occupying less than 20% of the silicon area and configured to detect faults at runtime in at least 80% of the plurality of transistors.

Automatic Error Diagnosis And Correction For Rtl Designs

View page
US Patent:
8365110, Jan 29, 2013
Filed:
May 27, 2008
Appl. No.:
12/127523
Inventors:
Kai-Hui Chang - Andover MA, US
Ilya Wagner - Bloomfield MI, US
Igor Markov - Ann Arbor MI, US
Valeria Bertacco - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G06F 9/455
G06F 17/50
US Classification:
716106, 716101, 716102, 716111, 716112, 716139, 717124, 717125, 717126, 717127
Abstract:
A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.

Field Repairable Logic

View page
US Patent:
20090089615, Apr 2, 2009
Filed:
Jul 23, 2008
Appl. No.:
12/178257
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
Ilya Wagner - Ann Arbor MI, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF MICHIGAN - Ann Arbor MI
International Classification:
G06F 11/00
US Classification:
714 23
Abstract:
A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time.

System For High-Efficiency Post-Silicon Verification Of A Processor

View page
US Patent:
20110087861, Apr 14, 2011
Filed:
Oct 12, 2010
Appl. No.:
12/902891
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Ilya Wagner - Hillsboro OR, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF MICHIGAN - Ann Arbor MI
International Classification:
G06F 9/302
US Classification:
712202, 712E09017
Abstract:
A post-silicon validation technique is able to craft randomized executable code, with known final outcomes, as a verification test that is executable on a hardware, such as a prototype microprocessor. A verification device is able to generate the test, in the form of programs, in such a way that at the end of the execution, the initial state of the test hardware is restored. Therefore, the final state of such a reversible program is known a priori. The technique may use a program generation algorithm, agnostic to any particular instruction set on the test hardware. In some examples, that algorithm is executed on the test hardware to generate the verification test, which is then executed on that test hardware. In other examples, the verification test is generated on another processor coupled to the test hardware. In either case, the verification test may contain initial and inverse operations determined from the test hardware.

Gate-Level Logic Simulator Using Multiple Processor Architectures

View page
US Patent:
20110257955, Oct 20, 2011
Filed:
Apr 21, 2010
Appl. No.:
12/764942
Inventors:
Valeria Bertacco - Ann Arbor MI, US
Debapriya Chatterjee - Ann Arbor MI, US
Andrew Deorio - Ann Arbor MI, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF MICHIGAN - Ann Arbor MI
International Classification:
G06F 17/50
US Classification:
703 15
Abstract:
Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.

Method And Apparatus For Determining Expected Values During Circuit Design Verification

View page
US Patent:
6493841, Dec 10, 2002
Filed:
Mar 31, 1999
Appl. No.:
09/283774
Inventors:
Won Sub Kim - Fremont CA
Valeria Maria Bertacco - Stanford CA
Daniel Marcos Chapiro - Palo Alto CA
Sandro Hermann Pintz - Menlo Park CA
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 3128
US Classification:
714741, 714739, 714 33, 703 17, 709310, 716 3
Abstract:
Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an âexpect,â for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUTs expected performance. In particular, upon the first occurrence of a transition on one of the DUTs nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUTs output is unexpected, or proceed with modeling the DUTs environment if the output is expected. A delay may be specified, which will delay the expects initiation of the window monitoring period.

Wikipedia References

Valeria Bertacco Photo 2

Valeria Bertacco

Isbn (Books And Publications)

Scalable Hardware Verification with Symbolic Simulation

View page
Author

Valeria Bertacco

ISBN #

0387244115

Scalable Hardware Verification with Symbolic Simulation

View page
Author

Valeria Bertacco

ISBN #

0387299068

Control profile
Valeria M Bertacco from Ann Arbor, MI, age ~54 Get Report