Utpal Mahanta

1745 north Ukiah Way, Upland, CA 91784

Semiconductors

Apple
Asic Design Engineer
Cadence Design Systems Jun 1, 2015 - Jun 2019
Principal Design Engineer
Lsi Corporation Apr 2009 - Jul 2013
Asic Design Engineer
Motorola Jul 2008 - Feb 2009
Software Developement Engineer

Purdue University 2013 - 2015
Masters, Computer Engineering Birla Institute of Technology and Science, Pilani 2004 - 2008
Bachelor of Engineering, Bachelors, Electronics

Verilog
Vlsi
C
Asic
Computer Architecture
Algorithms
Soc
Embedded Systems
C++
Static Timing Analysis
Tcl
Software Development
Debugging
System Verilog
Soc Design
Sta
Physical Design
Fpga
Rtl Design
Ddr Phy
Ddrx Gddrx Hbm
Python
Dft
Timing Closure
Universal Verification Methodology
Cache Coherency
Logic Design
Rtl Coding
Low Power Design
Synthesis
High Speed Digital Design
Serdes
Microarchitecture
Eda
Axi/Ahb/Apb
Jedec
Dfi
Dram

Purdue University

Jan 2014 to 2000
Graduate Teaching Assistant, EE337 - ASIC Design Lab
LSI
Bangalore, Karnataka
Apr 2009 to Jul 2013
ASIC Design Engineer
Motorola
Hyderabad, Andhra Pradesh
Jul 2008 to Feb 2009
Software Development Engineer

Purdue University
West Lafayette, IN
2013 to 2015
MS in Electrical and Computer Engineering
Birla Institute of Technology and Science
Aug 2004 to May 2008
BE in Electronics and Instrumentation

Hardware Design , ASIC/SoC Design, Hardware Software Partitioning, STA, Algorithims, Computer Architecture, Physical Design<br/><br/>Software Skills<br/> IC Design - ICCompiler (ICC), Primetime, Calibre, Spyglass, Redhawk, Quartus, ModelSim, Design Compiler(DC)<br/> Scripting languages - Tcl, Python<br/> Programming Languages/Packages - C/C++, Verilog, System Verilog, OpenCL