Resumes
Resumes
Sr. Automation & Controls Engineer At Genzyme
View pagePosition:
Sr. Automation & Controls Engineer at Genzyme
Location:
Framingham, Massachusetts
Industry:
Biotechnology
Work:
Genzyme - Greater Boston Area since Jul 2012
Sr. Automation & Controls Engineer
AstraZeneca Pharmaceuticals Mar 2003 - Jul 2012
Sr.Controls and Automation Engineer
AstraZeneca Mar 2003 - Jul 2012
Sr.Process Engineer
ValSource, LLC Mar 2003 - Sep 2005
Validation Specialist
AstraZeneca Pharmaceuticals 2003 - Jan 2005
Sr.Process Engineer
Sr. Automation & Controls Engineer
AstraZeneca Pharmaceuticals Mar 2003 - Jul 2012
Sr.Controls and Automation Engineer
AstraZeneca Mar 2003 - Jul 2012
Sr.Process Engineer
ValSource, LLC Mar 2003 - Sep 2005
Validation Specialist
AstraZeneca Pharmaceuticals 2003 - Jan 2005
Sr.Process Engineer
Education:
Manipal Institute of Technology 1994 - 1998
B.E, Computer Science
B.E, Computer Science
Skills:
C++
Oracle
Microsoft SQL Server
.NET
C
TWS
Visual C++
Ladder Logic
Validation
21 CFR Part 11
GMP
Change Control
Computer System Validation
FDA
Pharmaceutical Industry
Quality Assurance
GAMP
Technology Transfer
GxP
CAPA
Automation
V&V
Project Management
Biotechnology
Sop
Oracle
Microsoft SQL Server
.NET
C
TWS
Visual C++
Ladder Logic
Validation
21 CFR Part 11
GMP
Change Control
Computer System Validation
FDA
Pharmaceutical Industry
Quality Assurance
GAMP
Technology Transfer
GxP
CAPA
Automation
V&V
Project Management
Biotechnology
Sop
Interests:
New technology, Programming
Senior Video Signal Processing Engineer
View pageLocation:
201 east Chapman Ave, Placentia, CA 92870
Industry:
Computer Hardware
Work:
Flir Systems
Senior Video Signal Processing Engineer
University of Hawaii at Manoa
Image Processing Engineer
On Semiconductor Jan 2015 - Jun 2016
Principal Engineer, Digital
Aptina Sep 2012 - Jul 2014
Staff Design Engineer
Aptina Jan 2009 - Aug 2012
Senior Product Architect
Senior Video Signal Processing Engineer
University of Hawaii at Manoa
Image Processing Engineer
On Semiconductor Jan 2015 - Jun 2016
Principal Engineer, Digital
Aptina Sep 2012 - Jul 2014
Staff Design Engineer
Aptina Jan 2009 - Aug 2012
Senior Product Architect
Education:
University of Hawaii at Manoa 2016 - 2019
Master of Education, Masters Case Western Reserve University 1991 - 1993
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Delhi 1988 - 1989
Masters, Master of Technology, Electrical Engineering
Master of Education, Masters Case Western Reserve University 1991 - 1993
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Delhi 1988 - 1989
Masters, Master of Technology, Electrical Engineering
Skills:
Noise Reduction
Microarchitecture
Verilog
Debugging
Python
Noise Cancellation
Shell Scripting
Semiconductors
Standard Cell
Soc
Asic
Fpga
Algorithms
System on A Chip
Embedded Systems
Application Specific Integrated Circuits
Field Programmable Gate Arrays
Analog
Rtl Design
Integrated Circuits
Mixed Signal
Low Power Design
Processors
Image Processing
Microarchitecture
Verilog
Debugging
Python
Noise Cancellation
Shell Scripting
Semiconductors
Standard Cell
Soc
Asic
Fpga
Algorithms
System on A Chip
Embedded Systems
Application Specific Integrated Circuits
Field Programmable Gate Arrays
Analog
Rtl Design
Integrated Circuits
Mixed Signal
Low Power Design
Processors
Image Processing
Languages:
Hindi
Kannada
French
Tamil
Kannada
French
Tamil