Resumes
Resumes
Uma Durairajan Phones & Addresses
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486 Leyte Ter, Sunnyvale, CA 94089
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Santa Clara, CA
Publications
Us Patents
Efficient Method Of Replicate Memory Data With Virtual Port Solution
View pageUS Patent:
20120051131, Mar 1, 2012
Filed:
Aug 30, 2010
Appl. No.:
12/871450
Inventors:
Zhen Liu - Redwood City CA, US
Uma Durairajan - Redwood City CA, US
Kenway Tam - Redwood City CA, US
Uma Durairajan - Redwood City CA, US
Kenway Tam - Redwood City CA, US
Assignee:
ORACLE INTERNATIONAL CORPORATION - Redwood City CA
International Classification:
G11C 16/04
US Classification:
36518505
Abstract:
A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, and includes a single read port for outputting the data. The hardware arrangement includes a modified sense amplifier (SA) configured to receive the data output on the single read port, and directly receive the plurality of decoded uncommon memory address portions. The plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA. Data output from the memory bitcell is forwarded when the modified SA is enabled.
Single "A" Latch With An Array Of "B" Latches
View pageUS Patent:
20230005560, Jan 5, 2023
Filed:
Sep 9, 2022
Appl. No.:
17/942059
Inventors:
- Palo Alto CA, US
Uma DURAIRAJAN - San Jose CA, US
Dinesh R. AMIRTHARAJ - Milpitas CA, US
Uma DURAIRAJAN - San Jose CA, US
Dinesh R. AMIRTHARAJ - Milpitas CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G11C 29/32
G11C 29/42
G11C 29/12
G11C 7/10
G11C 29/36
G11C 29/42
G11C 29/12
G11C 7/10
G11C 29/36
Abstract:
An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.
Configurable Embedded Memory System
View pageUS Patent:
20140133246, May 15, 2014
Filed:
Nov 9, 2012
Appl. No.:
13/673892
Inventors:
Xilinx, Inc. - , US
James M. Simkins - Park City UT, US
Thomas H. Strader - Corona CA, US
Matthew H. Klein - Redwood City CA, US
James E. Ogden - Tracy CA, US
Uma Durairajan - Sunnyvale CA, US
James M. Simkins - Park City UT, US
Thomas H. Strader - Corona CA, US
Matthew H. Klein - Redwood City CA, US
James E. Ogden - Tracy CA, US
Uma Durairajan - Sunnyvale CA, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G11C 7/10
G11C 8/00
G11C 8/00
US Classification:
36518902, 36523003
Abstract:
An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.