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Trevor Nigel Mudge

from Ann Arbor, MI
Age ~76
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Also known as:
Trevor N Mudge, Trevor N Vanvalkenburg, Trevor N Madge, Mudge Trevor
Phone and address:
3801 Wynnstone Dr, Ann Arbor, MI 48105
(734) 995-2044
Related to:
Iulian Mioc, 69Emilia Mioc, 64Julian Mioc
Connected to:
Betty J Mudge, 80Bonnie L Mudge, 53Calvin L Mudge, 36Chris A Mudge, 50Dawn M Mudge, 49Gail M Mudge, 74Gary L Mudge, 82Gloria V Mudge, 40Gregory A Mudge, 71Jack R Mudge, 24

Trevor Mudge Phones & Addresses

  • 3801 Wynnstone Dr, Ann Arbor, MI 48105 (734) 995-2044
  • 3801 Wynnstone Dr, Ann Arbor, MI 48105 (734) 476-0229

Work

Position: Financial Professional

Education

Degree: Graduate or professional degree

Emails

a***[email protected]

Resumes

Resumes

Trevor Mudge Photo 1

Bredt Family Professor Of Computer Engineering At The University Of Michigan

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Location:
Ann Arbor, MI
Industry:
Research
Work:
Arm Jan 2007 - Sep 2007
Visiting Professor
University of Michigan Jan 2007 - Sep 2007
Bredt Family Professor of Computer Engineering at the University of Michigan
Education:
University of Illinois at Urbana - Champaign 1969 - 1977
Doctorates, Doctor of Philosophy, Computer Science Bancrofts School
Skills:
Computer Architecture
Algorithms
Computer Science
Parallel Computing
High Performance Computing
Machine Learning
Simulations
Latex
Embedded Systems
C++
Distributed Systems
Signal Processing
C
Fpga
Programming
Python
Software Engineering
Image Processing
Artificial Intelligence
Computer Vision
System Architecture
Parallel Programming
Perl
Matlab
Semiconductors
Scientific Computing
Trevor Mudge Photo 2

Trevor Mudge

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Trevor Mudge
Director
Regents of The University of Michigan
University · Accounting/Auditing/Bookkeeping College/University · Labor Organizations
1205 Beal Ave, Ann Arbor, MI 48109
(734) 647-5486, (734) 763-2243, (734) 764-6474

Publications

Us Patents

Memory System Having Fast And Slow Data Reading Mechanisms

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US Patent:
6944067, Sep 13, 2005
Filed:
Feb 18, 2004
Appl. No.:
10/779809
Inventors:
Trevor Nigel Mudge - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Dennis Michael Sylvester - Ann Arbor MI, US
Krisztian Flautner - Cambridge, GB
Assignee:
ARM Limited - Cambridge
International Classification:
G11C007/00
US Classification:
36518907, 36518905, 365194
Abstract:
There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said, fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

Data Processor Memory Circuit

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US Patent:
7055007, May 30, 2006
Filed:
Apr 10, 2003
Appl. No.:
10/410602
Inventors:
Krisztian Flautner - Cambridge, GB
David T. Blaauw - Ann Arbor MI, US
Trevor N. Mudge - Ann Arbor MI, US
Nam S. Kim - Ann Arbor MI, US
Steven M. Martin - Ann Arbor MI, US
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 12/00
US Classification:
711156, 711137
Abstract:
A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

Memory System Having Fast And Slow Data Reading Mechanisms

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US Patent:
7072229, Jul 4, 2006
Filed:
Jun 13, 2005
Appl. No.:
11/150585
Inventors:
Todd Michael Austin - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Trevor Nigel Mudge - Ann Arbor MI, US
Dennis Michael Sylvester - Ann Arbor MI, US
Krisztian Flautner - Cambridge, GB
Assignee:
ARM Limited - Cambridge
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G11C 7/00
US Classification:
36518907, 36518905, 365194
Abstract:
There is provided a memory for storing data comprising:.

Performance Level Selection In A Data Processing System Using A Plurality Of Performance Request Calculating Algorithms

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US Patent:
7131015, Oct 31, 2006
Filed:
Oct 20, 2003
Appl. No.:
10/687972
Inventors:
Krisztian Flautner - Cambridge, GB
Trevor Nigel Mudge - Ann Arbor MI, US
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 1/32
US Classification:
713320
Abstract:
Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.

Systematic And Random Error Detection And Recovery Within Processing Stages Of An Integrated Circuit

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US Patent:
7162661, Jan 9, 2007
Filed:
Feb 18, 2004
Appl. No.:
10/779805
Inventors:
Trevor Nigel Mudge - Ann Arbor MI, US
Todd Michael Austin - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Krisztian Flautner - Cambridge, GB
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 11/10
US Classification:
714 10, 714746, 714819
Abstract:
An integrated circuit includes a plurality of processing stages each including processing logic , a non-delayed signal-capture element , a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Performance Level Setting Of A Data Processing System

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US Patent:
7194385, Mar 20, 2007
Filed:
Oct 20, 2003
Appl. No.:
10/687928
Inventors:
Krisztian Flautner - Cambridge, GB
Trevor Nigel Mudge - Ann Arbor MI, US
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 11/30
US Classification:
702186, 702178
Abstract:
A target processor performance level is calculated from a utilisation history of a processor in performance of a plurality of processing tasks. The method comprises calculating a task work value indicating processor utilisation in performing a given processing task within a predetermined task time-interval and calculating a target processor performance level in dependence upon the task work value.

Data Processor Memory Circuit

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US Patent:
7260694, Aug 21, 2007
Filed:
Sep 26, 2006
Appl. No.:
11/526687
Inventors:
Krisztian Flautner - Cambridge, GB
Trevor N. Mudge - Ann Arbor MI, US
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 12/00
US Classification:
711156
Abstract:
A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

Error Detection And Recovery Within Processing Stages Of An Integrated Circuit

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US Patent:
7278080, Oct 2, 2007
Filed:
Mar 20, 2003
Appl. No.:
10/392382
Inventors:
Krisztian Flautner - Cambridge, GB
Todd Michael Austin - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Trevor Nigel Mudge - Ann Arbor MI, US
Assignee:
ARM Limited - Cambridge
University of Michigan - Ann Arbor MI
International Classification:
G06F 11/10
US Classification:
714746, 714 10, 714819
Abstract:
An integrated circuit includes a plurality of processing stages each including processing logic , a non-delayed latch , a delayed latch and a comparator. The non-delayed latch captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed latch also captures a value from the processing logic. The comparator compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a maimer that increases overall performance.

Isbn (Books And Publications)

Proceedings of the 1992 International Conference on Parallel Processing: August 17-21, 1992

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Author

Trevor N. Mudge

ISBN #

0849307805

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Trevor Nigel Mudge from Ann Arbor, MI, age ~76 Get Report