Toney C Warren

48499935, Jul 18, 1989

Dec 10, 1987

7/131141

Steven Johnson - Walnut Creek CA
Toney Warren - Livermore CA

Silicon General, Inc. - San Jose CA

H04L 708

375108

The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored.

49339559, Jun 12, 1990

Feb 26, 1988

7/161019

Toney Warren - Livermore CA
Steven Johnson - Walnut Creek CA

Silicon General, Inc. - San Jose CA

H04L 704

375 20

The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.

44687672, Aug 28, 1984

Dec 7, 1981

6/328316

Toney C. Warren - Clayton CA
Michael E. Hance - Concord CA

Coastcom - Concord CA

H04J 308

370 55

Apparatus for dropping and inserting digital data in a time division multiplexed, serial data stream. A communications link is divided into two spans with an electrical switch connecting the two spans. Data is used to derive channel-timing information defining the time divisions or strobes of each of the multiplexed channels. The strobe pulses are used to toggle the switch so that local transmit-and-receive channels may be inserted and dropped in accord with the channel strobe pulses. The same channel strobe pulses used for transmitting local data are used for receiving data from the multiplexed bit stream. In the absence of channel strobe pulses, the switch connects the two links.