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Todd W Bystrom

from Los Altos, CA
Age ~56
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Also known as:
Todd Te Bystrom, Todd C Bystrom, Todd W Rystrom, Todd W Bystom
Phone and address:
910 Odell Way, Los Altos, CA 94024
(650) 938-4293
Related to:
Evelyn Yolanda Martinez, 45Kyle Bystrom, 28Stacey L Mullen, 58Marlis R Bystrom, 83Julie Mullen, 64Lynn D Mullen, 70Cheryl L Bystrom, 58William L Bystrom, 84
Connected to:
Cynthia J Bystrom, 73Dianne J Bystrom, 67Lotta E Bystrom, 68Lyndon C Bystrom, 44Rene Bystron, 37Aleksandr S Bystrov, 65Alex V Bystrov, 41Anna Bystrova, 41Dariusz Bystrowski, 43Frank J Bystrycki, 69

Todd Bystrom Phones & Addresses

  • 910 Odell Way, Los Altos, CA 94024 (650) 938-4293
  • 1077 Freestone Ave, Sunnyvale, CA 94087 (408) 773-1618
  • Huntington Beach, CA
  • Helton, KY
  • Costa Mesa, CA
  • Santa Clara, CA
  • 910 Odell Way, Los Altos, CA 94024 (408) 406-0566

Work

Position: Professional/Technical

Emails

t***[email protected]

Publications

Us Patents

Method And Apparatus For Configuring Access Times Of Memory Devices

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US Patent:
6842864, Jan 11, 2005
Filed:
Oct 5, 2000
Appl. No.:
09/685014
Inventors:
Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos Hills CA, US
Todd W. Bystrom - Sunnyvale CA, US
Bradley A. May - San Jose CA, US
Paul G. Davis - San Jose CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1300
US Classification:
713401, 713400, 713500, 713501, 713503, 713600, 714700, 714719, 714721, 711170, 711167, 711105, 365233
Abstract:
A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

Pll Lock Detection Circuit Using Edge Detection

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US Patent:
6879195, Apr 12, 2005
Filed:
Jul 17, 2003
Appl. No.:
10/622627
Inventors:
Michael Green - Carlsbad CA, US
Nhat M. Nguyen - San Jose CA, US
Yohan Frans - Palo Alto CA, US
Dennis Kim - San Francisco CA, US
Todd Bystrom - Los Altos CA, US
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
H03L007/06
US Classification:
327147, 327156
Abstract:
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

Pll Lock Detection Circuit Using Edge Detection And A State Machine

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US Patent:
7084681, Aug 1, 2006
Filed:
Mar 23, 2005
Appl. No.:
11/088152
Inventors:
Michael Green - Carlsbad CA, US
Nhat M. Nguyen - San Jose CA, US
Yohan Frans - Palo Alto CA, US
Dennis Kim - San Francisco CA, US
Todd Bystrom - Los Altos CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03L 7/06
US Classification:
327147, 327156
Abstract:
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

System And Module Including A Memory Device Having A Power Down Mode

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US Patent:
7571330, Aug 4, 2009
Filed:
May 25, 2005
Appl. No.:
11/137469
Inventors:
Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos Hills CA, US
Todd W. Bystrom - Sunnyvale CA, US
Bradley A. May - San Jose CA, US
Paul G. Davis - San Jose CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1/00
G06F 13/00
US Classification:
713300, 713323, 711167
Abstract:
A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

Memory Device Having A Power Down Exit Register

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US Patent:
7574616, Aug 11, 2009
Filed:
Sep 17, 2004
Appl. No.:
10/944320
Inventors:
Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos Hills CA, US
Todd W. Bystrom - Sunnyvale CA, US
Bradley A. May - San Jose CA, US
Paul G. Davis - San Jose CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1/26
US Classification:
713320, 711105, 711167
Abstract:
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

System For A Memory Device Having A Power Down Mode And Method

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US Patent:
7581121, Aug 25, 2009
Filed:
Jun 14, 2005
Appl. No.:
11/151791
Inventors:
Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos CA, US
Todd W. Bystrom - Sunnyvale CA, US
Bradley A. May - San Jose CA, US
Paul G. Davis - San Jose CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1/00
G06F 13/00
US Classification:
713300, 713323, 711167
Abstract:
A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

Clock-Data Recovery (“Cdr”) Circuit, Apparatus And Method For Variable Frequency Data

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US Patent:
7668271, Feb 23, 2010
Filed:
Sep 30, 2003
Appl. No.:
10/675027
Inventors:
Dennis Kim - San Francisco CA, US
Jason Wei - Cupertino CA, US
Yohan Frans - Palo Alto CA, US
Todd Bystrom - Los Altos CA, US
Nhat Nguyen - San Jose CA, US
Kevin Donnelly - Los Altos CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 7/00
US Classification:
375354
Abstract:
A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

Method Of Operation Of A Memory Device And System Including Initialization At A First Frequency And Operation At A Second Frequency And A Power Down Exit Mode

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US Patent:
8127152, Feb 28, 2012
Filed:
Nov 19, 2004
Appl. No.:
10/993046
Inventors:
Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos Hills CA, US
Todd W. Bystrom - Sunnyvale CA, US
Bradley A. May - San Jose CA, US
Paul G. Davis - San Jose CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
G06F 1/00
G06F 13/00
US Classification:
713300, 713320, 713400, 713401, 713500, 711167, 711170, 711105, 711154, 3652331, 365226, 365194
Abstract:
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
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Todd W Bystrom from Los Altos, CA, age ~56 Get Report