US Patent:
20220262427, Aug 18, 2022
Inventors:
- Santa Clara CA, US
Virendra Vikramsinh Adsure - Folsom CA, US
Jaya Jeyaseelan - Campbell CA, US
Nadav Bonen - Ofer Z, IL
Barnes Cooper - Hillsboro OR, US
Toby Opferman - Portland OR, US
Chia-Hung Kuo - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/406
G11C 5/14
G11C 11/4074
G11C 11/402
Abstract:
A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.
