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Tito D Gelsomini

from Plano, TX
Age ~87
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Also known as:
Pito Gelsomini
Phone and address:
1313 Newbury Ln, Plano, TX 75025
(972) 527-5419
Related to:
Robin S Woolery, 63Joanne T Sanders, 80Granam Beer, 47Graham B Beer, 77Judith Beer, 76Beverly Adair, 78James Shea
Connected to:
Anthony S Gelsomino, 45Laura M Gelsomino, 73Laura A Gelsomini, 63Thomas H Gelsomino, 33Gay G Gelson, 64Gene F Gelsone, 82Martin R Gelsthorpe, 71Barry B Gelston, 63Fred H Gelston, 77Beth M Gelt, 85

Tito Gelsomini Phones & Addresses

  • 1313 Newbury Ln, Plano, TX 75025 (972) 527-5419
  • 3323 El Dorado Blvd, Missouri City, TX 77459 (281) 261-8685
  • Sugar Land, TX
  • Anna, TX
  • 1313 Newbury Ln, Plano, TX 75025 (972) 768-5775

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: High school graduate or higher

Publications

Us Patents

Integrated Circuit Wireless Tagging

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US Patent:
6368901, Apr 9, 2002
Filed:
Mar 8, 2001
Appl. No.:
09/800519
Inventors:
Tito Gelsomini - Plano TX
Giulio G. Marotta - Contigliano, IT
Sebastiano DArrigo - Cannes, FR
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2182
US Classification:
438131, 438907
Abstract:
A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Chip Identifier And Method Of Fabrication

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US Patent:
6456554, Sep 24, 2002
Filed:
Oct 11, 2000
Appl. No.:
09/686455
Inventors:
Tito Gelsomini - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 700
US Classification:
365226, 36518901, 36518912
Abstract:
An integrated circuit chip comprising an integrated circuit made in a semiconductor substrate, an information write-register circuit having a plurality of gate-controlled components, such as MOS transistors or capacitors, said write-register being integrated into said circuit yet individually addressable; said components having a gate insulator geometry locally susceptible to electrical conductivity upon applying overstress voltage pulses between said gates and said substrate, whereby information can be permanently encoded into said write-register; and a plurality of level shifter circuits to supply said pulses selectively to said component gates according to stored data and controlled by enable commands, said level shifters being integrated into said circuit.

Integrated Circuit Wireless Tagging

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US Patent:
6525410, Feb 25, 2003
Filed:
Jul 15, 1999
Appl. No.:
09/354262
Inventors:
Tito Gelsomini - Plano TX
Giulio G. Marotta - Contigliano, IT
Sebastiano DArrigo - Cannes, FR
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2302
US Classification:
257678, 257664, 257734, 434855
Abstract:
A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Anti-Fuse Structure Of Writing And Reading In Integrated Circuits

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US Patent:
6611040, Aug 26, 2003
Filed:
Jun 2, 2001
Appl. No.:
09/873035
Inventors:
Tito Gelsomini - Plano TX, 75025
Kemal Tamer San - Plano TX, 75075
International Classification:
H01L 2900
US Classification:
257530, 257529, 257528, 438131, 438167, 438600, 438957, 365226, 3652257, 36518901, 36518902
Abstract:
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Anti-Fuse Structure And Method Of Writing And Reading In Integrated Circuits

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US Patent:
6781887, Aug 24, 2004
Filed:
Jun 5, 2003
Appl. No.:
10/455579
Inventors:
Tito Gelsomini - Plano TX
Kemal Tamer San - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 1604
US Classification:
36518901, 36518912
Abstract:
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Transistor Design Self-Aligned To Contact

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US Patent:
7429524, Sep 30, 2008
Filed:
Sep 14, 2005
Appl. No.:
11/225992
Inventors:
Andrew Marshall - Dallas TX, US
Tito Gelsomini - Plano TX, US
Harvey Edd Davis - Trenton TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/3205
H01L 21/4763
US Classification:
438585, 438618, 438279
Abstract:
The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure () over a substrate (). An insulating layer () is formed over the gate structure (), and openings () to the substrate () are formed therein, thereby removing a portion of the gate structure (). The openings () are filled with a conductor (), thereby forming an interconnect ().

Method For Testing Transistors Having An Active Region That Is Common With Other Transistors And A Testing Circuit For Accomplishing The Same

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US Patent:
7499354, Mar 3, 2009
Filed:
Nov 8, 2005
Appl. No.:
11/268974
Inventors:
Theodore W. Houston - Richardson TX, US
Xiaowei Deng - Plano TX, US
Tito Gelsomini - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 7/00
US Classification:
365201, 365200, 36518908
Abstract:
The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors () located within a common active region, and biasing a terminal () between the pair () relative to gates () of the pair () and terminals () outlying the pair () to obtain a leakage current associated with the pair ().

Merged Camera And Scanner

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US Patent:
7679792, Mar 16, 2010
Filed:
Dec 16, 2005
Appl. No.:
11/305520
Inventors:
Andrew Marshall - Dallas TX, US
Tito Gelsomini - Plano TX, US
Harvey Edd Davis - Trenton TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 1/04
H04N 1/46
US Classification:
358474, 358505
Abstract:
A narrow scanning aperture, lens, and mirror are added to a digital camera to enable image or text scanning. A motion sensor on the same face as the scanner aperture provides approximate scan speed data as the scanner aperture is pressed against and manually moved across the document being scanned. Many documents are too large to scan in one strip, in which case multiple strips are scanned. As each strip is scanned, a bit-mapped image of the strip is created in a data buffer. Data from each strip is passed to a final image RAM which, on completion of scanning, holds a bit-mapped image of the entire scanned page, in B/W, gray scale, or color. Multi pass strip align then processes the image data to remove redundant data (from strip overlap) and position skew (from errors in position during the scan), resulting in a more accurate bit-mapped image in final image RAM of the entire scanned page or item. Image compression compresses the bit-mapped image to standard JPEG format for storage on the camera memory card. An alternative embodiment stores each scanned strip as a separate image.
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Tito D Gelsomini from Plano, TX, age ~87 Get Report