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Timothy Swettlen Phones & Addresses

  • Vancouver, WA
  • 828 NW Summit Ave, Portland, OR 97210
  • Ruffs Dale, PA
  • 4808 146Th St, Seattle, WA 98168
  • Tukwila, WA
  • 620 Peninsula Ave #B, Burlingame, CA 94010
  • San Francisco, CA
  • Santa Clara, CA
  • Phoenix, AZ
  • Kokomo, IN
  • Chandler, AZ
  • San Jose, CA

Publications

Us Patents

Mechanism To Stabilize Power Delivered To A Device Under Test

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US Patent:
20050285613, Dec 29, 2005
Filed:
Jun 24, 2004
Appl. No.:
10/875874
Inventors:
Arthur Isakharov - Hillsboro OR, US
Isaac Chang - Subang Jaya, MY
Ai Ssa Chai - Sungai Petani, MY
Timothy Swettlen - Tukwila WA, US
International Classification:
G01R031/26
US Classification:
324765000
Abstract:
According to one embodiment a system is disclosed. The system includes a tester having a power supply, an integrated circuit device under test (DUT) and a transient compressor (TC) coupled between the tester and the power supply to stabilize power delivered to the DUT by injecting current into the path between the power supply and the DUT.

Probe Card With Improved Transient Power Delivery

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US Patent:
20070145989, Jun 28, 2007
Filed:
Dec 27, 2005
Appl. No.:
11/318660
Inventors:
Hua Zhu - Campbell CA, US
Erich Chuh - Santa Clara CA, US
Timothy Swettlen - Tukwila WA, US
International Classification:
G01R 31/02
US Classification:
324754000
Abstract:
In high current integrated circuit wafer test applications, a high capacitance density capacitor may be formed in association with a probe card at a position closer to a wafer under test. This reduces the power path impedance, improving transient power delivery of a probe card. That is because now the capacitance is positioned more closely to the wafer under test, reducing path impedance. The capacitance density may be at higher, improving transient power delivery.

Shielding In Electronic Assemblies

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US Patent:
20190098802, Mar 28, 2019
Filed:
Sep 27, 2017
Appl. No.:
15/716757
Inventors:
- Santa Clara CA, US
Timothy Swettlen - Portland OR, US
Kevin Byrd - Lake Oswego OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 9/00
H05K 1/18
H05K 3/34
H01L 23/498
Abstract:
Disclosed herein are arrangements for shielding in electronic assemblies, as well as related methods and devices. In some embodiments, an electronic assembly may include a circuit board having a first face and a second opposing face, and a shield coupled to the second face of the circuit board. The circuit board may have a hole extending therethrough, and the shield may extend into the hole towards the first face.

Electromagnetic Interference (Emi) Shield For A Printed Circuit Board (Pcb)

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US Patent:
20190037683, Jan 31, 2019
Filed:
Jul 26, 2017
Appl. No.:
15/660481
Inventors:
- Santa Clara CA, US
Timothy Swettlen - Portland OR, US
International Classification:
H05K 1/02
H05K 9/00
H05K 1/18
G06F 1/16
Abstract:
Embodiments herein disclose techniques for electronic apparatuses including a printed circuit board (PCB) and an electromagnetic interference (EMI) shield for the PCB. An electronic apparatus may include a PCB with a plurality of layers including a ground layer. The PCB may include a cutout through the plurality of layers of the PCB. An EMI shield may be mounted to a bottom side of the PCB along an edge of the cutout, where the EMI shield may be coupled to the ground layer through an ohmic contact. The EMI shield may be flat. Other embodiments may also be described and claimed.

Systems And Methods For Replaceable Bail Grid Array (Bga) Packages On Board Substrates

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US Patent:
20190037708, Jan 31, 2019
Filed:
Apr 1, 2016
Appl. No.:
16/072367
Inventors:
- Santa Clara CA, US
Timothy SWETTLEN - Portland OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H05K 3/40
H01L 23/498
H05K 3/34
Abstract:
The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.

Interconnect Architecture With Stacked Flex Cable

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US Patent:
20160248210, Aug 25, 2016
Filed:
May 2, 2016
Appl. No.:
15/144677
Inventors:
- Santa Clara CA, US
Timothy M. SWETTLEN - Portland OR, US
Gary B. LONG - Aloha OR, US
Donald T. TRAN - Phoenix AZ, US
Jill D. MURFIN - Hillsboro OR, US
David I. AMIR - Portland OR, US
International Classification:
H01R 43/02
H01R 43/20
Abstract:
Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.

Interconnect Architecture With Stacked Flex Cable

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US Patent:
20140273552, Sep 18, 2014
Filed:
Mar 15, 2013
Appl. No.:
13/844501
Inventors:
Sanka GANESAN - Chandler AZ, US
Timothy M. SWETTLEN - Portland OR, US
Gary B. LONG - Aloha OR, US
Donald T. TRAN - Phoenix AZ, US
Jill D. MURFIN - Hillsboro OR, US
David D. AMIR - Portland OR, US
International Classification:
H05K 1/14
US Classification:
439 65
Abstract:
Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.
Timothy M Swettlen from Vancouver, WA, age ~51 Get Report