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Timothy L Michalka

from San Diego, CA
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Also known as:
Tim Michalka, T Michalka
Phone and address:
12619 El Camino Real UNIT A, San Diego, CA 92130
(858) 792-0049
Related to:
Kyle Michalka, 64Susan E Michalka, 65Kyle R Michalka, 38Alexander D Michalka, 40
Connected to:
Agatha A Michalik, 37Ann M Michalk, 51Artur R Michalik, 46Beth Michalik, 59Bryan E Michalic, 45Chester J Michalik, 89Daniel Z Michalk, 90David W Michalke, 68Eric J Michalik, 51Eugene Michali, 70

Timothy Michalka Phones & Addresses

  • 12619 El Camino Real UNIT A, San Diego, CA 92130 (858) 792-0049
  • 12619 El Camino Real, San Diego, CA 92130
  • Fort Collins, CO

Interests

job inquiries, getting back in touch

Industries

Telecommunications

Resumes

Resumes

Timothy Michalka Photo 1

Principal Eng/Mgr At Qualcomm

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Location:
Greater San Diego Area
Industry:
Telecommunications
Experience:
Qualcomm (Public Company; 10,001 or more employees; QCOM; Telecommunications industry): Principal Eng/Mgr,  (-) Hewlett-Packard (Public Company; HPQ; Information Technology and Services industry): Project Manager,  (August 1996-July 2005) Microprocessor ...

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Hollywood: Writer(s) Aly Michalka, AJ Michalka, Timothy A. James, Antonina Armato: Certification: Gold : Aly & AJ main singles chronology "

Us Patents

Four-Drop Bus With Matched Response

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US Patent:
6744332, Jun 1, 2004
Filed:
Jun 21, 2002
Appl. No.:
10/176833
Inventors:
Karl Joseph Bois - Fort Collins CO
David W. Quint - Fort Collins CO
Timothy L. Michalka - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H01P 512
US Classification:
333125
Abstract:
A four-drop bus has each driver or receiver terminated at the characteristic impedance of Z. Each driver or receiver is connected to a segment of transmission line with a characteristic impedance of Z. Two of these segments are connected at a first point. The other two of these segments are connected at a second point. The first and second points are connected by a central transmission line with a characteristic impedance of Z /2.

Package Routing Of Integrated Circuit Signals

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US Patent:
61612154, Dec 12, 2000
Filed:
Aug 31, 1998
Appl. No.:
9/144299
Inventors:
David B. Hollenbeck - Fort Collins CO
William S. Worley - Denver CO
David W. Quint - Fort Collins CO
Timothy L. Michalka - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1750
US Classification:
716 15
Abstract:
Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

Printed Circuit Board Substrate And Method For Constructing Same

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US Patent:
20080196933, Aug 21, 2008
Filed:
Apr 16, 2008
Appl. No.:
12/148017
Inventors:
Karl Joseph Bois - Ft. Collins CO, US
Timothy L. Michalka - Ft. Collins CO, US
International Classification:
H01R 12/14
H05K 1/11
H05K 3/00
US Classification:
174261, 174257, 174258, 29829
Abstract:
A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A first signal path layer is embedded in the first dielectric material and a second signal path layer is embedded in the second dielectric material, wherein the first and second signal path layers are substantially parallel to each other in a stack-up arrangement. An adhesive layer is interposed between the first dielectric material and the second dielectric material.

Printed Circuit Board Substrate And Method For Constructing Same

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US Patent:
20050183883, Aug 25, 2005
Filed:
Feb 19, 2004
Appl. No.:
10/782640
Inventors:
Karl Bois - Ft. Collins CO, US
Timothy Michalka - Ft. Collins CO, US
International Classification:
H05K001/03
US Classification:
174255000, 174259000
Abstract:
A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A signal path layer is interposed between the first dielectric material and the second dielectric material. An adhesive layer is interposed between the first dielectric material and the second dielectric material such that the adhesive layer is substantially coplanar relative to the signal path layer.
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Timothy L Michalka from San Diego, CA Get Report