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Thomas Obkircher

from Santa Ana, CA
Age ~53
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Also known as:
Bircher O Thomas, Thomas R
Phone and address:
1542 Loma Verde Ln, Santa Ana, CA 92705
Related to:
Ramiro C Castillo, 63Rogelio G Gonzales, 61Edis A Castillo, 74Oscar Raul Padilla, 52Markus Obkircher, 51Maria Sandoval HernandezJessey K Castillo, 30Alma L Padilla, 54
Connected to:
Brian J Oblack, 64Ashley S Oblad, 41Andrew J Oblak, 94Ashley Oblak, 34Peter A Oblak, 66Todd G Oblak, 44John W Oblanas, 59Stephen Oblander, 81Deborah T Oblath, 68Jack K Oblaza, 73

Thomas Obkircher Phones & Addresses

  • 1542 Loma Verde Ln, Santa Ana, CA 92705
  • Placentia, CA
  • Newport Beach, CA
  • 2584 Sutter Ct, Tustin, CA 92782 (714) 832-1712
  • Orange, CA
  • 1542 Loma Verde Ln, Santa Ana, CA 92705 (714) 832-1712

Work

Company: Skyworks solutions, inc. May 2004 Position: Technical director

Education

School / High School: University of Southern California - Marshall School of Business 2002 to 2005

Industries

Semiconductors

Resumes

Resumes

Thomas Obkircher Photo 1

Thomas Obkircher

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Position:
Technical Director at Skyworks Solutions, Inc.
Location:
Orange County, California Area
Industry:
Semiconductors
Work:
Skyworks Solutions, Inc. since May 2004
Technical Director
Tekwiss USA Nov 2002 - May 2004
Co-Founder
Valence Nov 2001 - Nov 2002
Staff Engineer
Conexant Systems Jul 1997 - Nov 2001
Digital Staff Engineer
Education:
University of Southern California - Marshall School of Business 2002 - 2005
Eidgenössische Technische Hochschule Zürich 1994 - 1997
Eidgenössische Technische Hochschule Zürich 1991 - 1993

Publications

Us Patents

Systems And Methods For Providing A Clock Signal

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US Patent:
7956656, Jun 7, 2011
Filed:
Mar 4, 2010
Appl. No.:
12/717734
Inventors:
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
H03K 19/094
H03K 19/20
US Classification:
327116, 327119, 377 47, 377 48
Abstract:
Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.

Circuits, Systems, And Methods For Managing Automatic Gain Control In Quadrature Signal Paths Of A Receiver

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US Patent:
8126094, Feb 28, 2012
Filed:
Jan 7, 2009
Appl. No.:
12/349787
Inventors:
Jaleh Komaili - Irvine CA, US
John E. Vasa - Irvine CA, US
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
H04L 27/08
US Classification:
375345
Abstract:
A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

Dynamically Configurable Serial Data Communication Interface

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US Patent:
8135881, Mar 13, 2012
Filed:
Sep 27, 2010
Appl. No.:
12/891513
Inventors:
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
G06F 13/14
US Classification:
710 37, 710 3
Abstract:
A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Systems And Methods For Providing A Clock Signal

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US Patent:
8212593, Jul 3, 2012
Filed:
Jun 3, 2011
Appl. No.:
13/152745
Inventors:
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
H03K 19/094
H03K 19/20
US Classification:
327116, 327119, 377 47, 377 48
Abstract:
Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.

Circuit, Controller And Methods For Dynamic Estimation And Cancellation Of Phase And Gain Imbalances In Quadrature Signal Paths Of A Receiver

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US Patent:
8374297, Feb 12, 2013
Filed:
Sep 15, 2008
Appl. No.:
12/210229
Inventors:
Jaleh Komaili - Irvine CA, US
Thomas Obkircher - Tustin CA, US
William J. Domino - Yorba Linda CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03D 1/04
H03D 1/06
US Classification:
375346, 325316, 327310, 327384, 327551, 455296
Abstract:
A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.

Circuit, Controller And Methods For Dynamic Estimation And Cancellation Of Phase And Gain Imbalances In Quardrature Signal Paths Of A Receiver

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US Patent:
8374300, Feb 12, 2013
Filed:
Mar 22, 2012
Appl. No.:
13/427549
Inventors:
Thomas Obkircher - Tustin CA, US
William J. Domino - Yorba Linda CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03D 1/04
H03D 1/06
H03K 5/01
H03K 6/04
H04B 1/10
H04L 1/00
H04L 25/08
US Classification:
375346, 375285, 375316
Abstract:
A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.

Dynamically Configurable Serial Data Communication Interface

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US Patent:
8417836, Apr 9, 2013
Filed:
Mar 5, 2012
Appl. No.:
13/412011
Inventors:
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
G06F 3/00
G06F 13/42
US Classification:
710 3, 710 11, 710105
Abstract:
A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Phase-Locked Loop Lock Detect

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US Patent:
8456206, Jun 4, 2013
Filed:
Jun 20, 2011
Appl. No.:
13/164098
Inventors:
Ardeshir Namdar-Mehdiabadi - Ottawa, CA
Yong Hee Lee - Tustin CA, US
Thomas Obkircher - Tustin CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.
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Thomas Obkircher from Santa Ana, CA, age ~53 Get Report