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Thomas M Mnich

from Woodland Park, CO
Age ~68
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Also known as:
Thomas W Mnich, Tom M Mnich, Thomas M Mhich, Thomas M Minch
Phone and address:
1801 Navajo Trl, Woodland Park, CO 80863
(719) 687-1303
Related to:
Christopher M Mnich, 43Cheryl A Mnich, 40Trisha L Mnich, 42Diana L Mnich, 67
Connected to:
Adam Mnich, 71Dana L Mnich, 36Kevin J Mnich, 48Marek Mnich, 67Matthew Mnich, 63Monica Mnich, 64Robert J Mnich, 48Bernard J Mnichowicz, 80Theresa P Mnichowicz, 81Robert H Mnookin, 82

Thomas Mnich Phones & Addresses

  • 1801 Navajo Trl, Woodland Park, CO 80863 (719) 687-1303
  • Albuquerque, NM
  • 1801 Navajo Trl, Woodland Park, CO 80863

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Industries

Semiconductors

Resumes

Resumes

Thomas Mnich Photo 1

Sr. Engineer/Scientist At Ibm

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Location:
Colorado Springs, Colorado Area
Industry:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Thomas Mnich
CTO
Air Products and Chemicals Inc
Crude Petroleum and Natural Gas · Industrial Gases
2185 Executive Cir, Colorado Springs, CO 80906
(719) 540-8385

Publications

Us Patents

Low Power Consumption Integrated Circuit Delay Locked Loop And Method For Controlling The Same

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US Patent:
6346839, Feb 12, 2002
Filed:
Apr 3, 2000
Appl. No.:
09/542509
Inventors:
Thomas Michael Mnich - Woodland Park CO
Assignee:
Mosel Vitelic Inc. - Hsinchu
International Classification:
H03L 706
US Classification:
327158, 327149, 327153, 327161, 331 14, 331DIG 2, 36518907, 365233, 375376
Abstract:
A low power consumption delay locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase detector to the slow operating condition of the programmable delay. In a particular embodiment, this may be effectuated by incorporating at least one additional flip-flop section in the phase detector circuit and more than one such section may be utilized depending on the operating targets of maximum frequency and frequency range. By latching the phase detector outputs through the use of a fast/slow latch circuit, a minimum control pulse is defined which allows a unitized change on the voltage signals that control the programmable delay in a voltage controlled delay line. This also improves efficiency and reduces power consumption by eliminating switching current through transistors that control the voltage levels determining the programmable delay.

Current Steering Reduced Bitline Voltage Swing, Sense Amplifier

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US Patent:
6501696, Dec 31, 2002
Filed:
May 15, 2001
Appl. No.:
09/855411
Inventors:
Thomas M. Mnich - Woodland Park CO
John Eric Gross - Monument CO
Assignee:
Cypress Seminconductor Corp. - San Jose CA
International Classification:
G11C 700
US Classification:
365207, 365190, 365208
Abstract:
A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.

Level Shifting Circuit And Method

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US Patent:
6590420, Jul 8, 2003
Filed:
Dec 20, 2001
Appl. No.:
10/029370
Inventors:
Thomas M. Mnich - Woodland Park CO
Ryan T. Hirose - Colorado Springs CO
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 190175
US Classification:
326 68, 326 81
Abstract:
A circuit for shifting a signal from a first voltage level referenced to a first voltage reference, to a second voltage level referenced to a second voltage reference, while reducing the gate to source voltages on the output transistors. In one embodiment, the circuit includes six switches. A first switch receives the signal; a second switch receives an inverted representation of the signal; a third switch receives the output of the first switch; a fourth switch receives the output of the second switch; a fifth switch, referenced to the second voltage reference, has an input coupled with the output of the first switch and a control coupled with the output of the fourth switch; and a sixth switch, referenced to the second voltage reference, has an input coupled with the output of the second switch and has a control coupled with the output of the third switch. In one embodiment, when the third switch and the fourth switch are on, the signal is shifted to the second voltage level measured between the input of the fifth switch and the second voltage reference. The third and fourth switches act to prevent the gate to source voltage on the fifth and sixth switches from reaching a high voltage level, such as 10 volts.

Current Steering Reduced Bitline Voltage Swing, Sense Amplifier

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US Patent:
6707741, Mar 16, 2004
Filed:
Nov 27, 2002
Appl. No.:
10/305625
Inventors:
Thomas M. Mnich - Woodland Park CO
John Eric Gross - Monument CO
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 700
US Classification:
365207, 36518907, 36518909, 365190, 365204
Abstract:
A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.

Magnetic Memory Array Architecture

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US Patent:
7283384, Oct 16, 2007
Filed:
Mar 24, 2004
Appl. No.:
10/809134
Inventors:
Fredrick B. Jenne - Los Gatos CA, US
Eugene Y. Chen - Fremont CA, US
Thomas M. Mnich - Woodland Park CO, US
William L. Stevenson - Redwood City CA, US
Assignee:
Silicon Magnetic Systems - San Jose CA
International Classification:
G11C 11/00
US Classification:
365158, 365171, 365 55
Abstract:
An MRAM device is provided which includes an array of magnetic elements, a plurality of conductive lines configured to set magnetization states of the magnetic elements and circuitry configured to vary current applications along one or more of the conductive lines. In some cases, the MRAM device may additionally or alternatively include circuitry which is configured to terminate an application of current along one or more of the conductive lines before magnetization states of one or more magnetic elements selected for a write operation of the device are changed. In either case, a device is provided which includes an MRAM array and a first storage circuit comprising one or more magnetic elements, wherein the first storage circuit is configured to store parameter settings characterizing operations of the magnetic random access memory array within the magnetic elements. Methods for operating the devices provided herein are contemplated as well.

Dynamic Random Access Memory With Operational Sleep Mode

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US Patent:
52629988, Nov 16, 1993
Filed:
Aug 14, 1991
Appl. No.:
7/744989
Inventors:
Thomas M. Mnich - Woodland Park CO
William D. Miller - Colorado Springs CO
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365222
Abstract:
A dynamic memory device exhibits a sleep mode of operation, entered in response to a single externally-applied signal which need not be cycled. While in this sleep mode, the device does not respond to or require any of the usual DRAM control signals such a RAS, CAS, write enable, address inputs, data inputs, etc. , so all of these signals may be in a quiescent state. An internal refresh counter is used to generate row addresses while in the sleep mode, and timing for the internal refresh is provided by an internal oscillator. The memory device cycles through a sequence of row addresses for refresh while in this sleep mode, using an internal refresh address counter, and this sequence may be maintained without interruption if the sleep mode is reentered within a normal refresh period after exiting the sleep mode. Thus, a sleep-exception mode of operation is provided in which normal read or write cycles can be interposed between sleep mode periods, so the overall power drain is very low but normal access is maintained at a relatively active level.

High Speed Lossless Data Compression Method And Apparatus Using Side-By-Side Sliding Window Dictionary And Byte-Matching Adaptive Dictionary

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US Patent:
54733260, Dec 5, 1995
Filed:
Nov 5, 1992
Appl. No.:
7/972046
Inventors:
Gary L. Harrington - Colorado Springs CO
Thomas M. Mnich - Woodland Park CO
William D. Miller - Colorado Springs CO
Assignee:
CERAM Incorporated - Colorado Springs CO
International Classification:
H03M 730
US Classification:
341 51
Abstract:
A data compression and decompression method and apparatus utilizing a sliding window dictionary in combination with an adaptive dictionary. Incoming data moves through a buffer and is compared against both the sliding window dictionary and the adaptive dictionary, and matched data is replaced with a pointer to the dictionary entry. All incoming data is entered into the sliding window dictionary, but only data which satisfies certain criteria is entered into the adaptive dictionary.

Semiconductor Memory Device

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US Patent:
58285962, Oct 27, 1998
Filed:
Sep 26, 1996
Appl. No.:
8/723949
Inventors:
Hidekazu Takata - Nara-ken, JP
Thomas Mnich - Woodland Park CO
David Novosel - New Wilmington PA
Assignee:
Sharp Kabushiki Kaisha - Osaka
International Classification:
G11C 1122
US Classification:
365145
Abstract:
A semiconductor memory device includes a ferroelectric memory having a non-volatile operation mode and a volatile operation mode; an input terminal to which an input signal indicating a voltage level of a power source voltage is input; a first signal generating circuit outputting a first control signal for regulating activation and inactivation of the non-volatile operation mode to the ferroelectric memory; and a second signal generating circuit outputting a second control signal for regulating the activation and inactivation of the non-volatile operation mode to the first signal generating circuit, based on the input signal. The non-volatile operation mode and the volatile operation mode are automatically switched with each other in accordance with changes in the voltage level of the power source voltage under a first operation condition, and only the volatile operation mode is activated under a second operation condition.
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Thomas M Mnich from Woodland Park, CO, age ~68 Get Report