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Thomas M Maffitt

from Burlington, VT
Age ~67
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Also known as:
Tom M Maffitt, Tom B Maffitt
Related to:
Thomas F Anderson, 48
Connected to:
Allison J Maffitt, 65Kevar L Maffitt, 32Ted Maffitt, 42Barbara E Maffre, 52Blair A Maffris, 75Joseph D Maffris, 68Barbara A Maffucci, 64Edward A Maffuccio, 78Irene D Maffucci, 79Jenna A Maffucci, 33

Thomas Maffitt Phones & Addresses

  • Burlington, VT
  • 332 Flat Rock Rd, Charlotte, VT 05445

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job inquiries, expertise requests, refer...

Industries

Semiconductors

Resumes

Resumes

Thomas Maffitt Photo 1

Senior Engineer At Ibm, Senior Engineer At International Business Machines

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Location:
Burlington, Vermont Area
Industry:
Semiconductors
Experience:
IBM Public Company; Semiconductors industry: Senior Engineer,  (-) International Business Machines Public Company; Semiconductors industry: Senior Engineer,  (1979-Present) 

Publications

Us Patents

Voltage Controlled Transmission Line With Real-Time Adaptive Control

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US Patent:
6369671, Apr 9, 2002
Filed:
Mar 30, 1999
Appl. No.:
09/281412
Inventors:
Claude L. Bertin - South Burlington VT
Anthony R. Bonaccio - Shelburne VT
Howard L. Kalter - Colchester VT
Thomas M. Maffitt - Burlington VT
Jack A. Mandelman - Stormville NY
Edward J. Nowak - Essex Junction VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01P 1185
US Classification:
333164, 257599, 257600, 257601
Abstract:
A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.

Integrated Circuit Capacitor

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US Patent:
6437385, Aug 20, 2002
Filed:
Jun 29, 2000
Appl. No.:
09/607094
Inventors:
Claude L. Bertin - South Burlington VT
Thomas M. Maffitt - Burlington VT
Wilbur D. Pricer - Charlotte VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27108
US Classification:
257301, 257302
Abstract:
Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.

Automatic Off-Chip Driver Adjustment Based On Load Characteristics

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US Patent:
6496037, Dec 17, 2002
Filed:
Jun 6, 2000
Appl. No.:
09/588202
Inventors:
Claude L. Bertin - South Burlington VT
John A. Fifield - Underhill VT
Thomas M. Maffitt - Burlington VT
Wilbur D. Pricer - Charlotte VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 190175
US Classification:
326 82, 326 30
Abstract:
An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.

Oxide Tracking Voltage Reference

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US Patent:
6522154, Feb 18, 2003
Filed:
Mar 16, 2001
Appl. No.:
09/811096
Inventors:
John Atkinson Fifield - Underhill VT
Mark David Jacunski - Colchester VT
Thomas Martin Maffitt - Burlington VT
Nicholas Van Heel - Eagle ID
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 2726
US Classification:
324678, 324522
Abstract:
A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method includes the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.

Dram Word Line Voltage Control To Insure Full Cell Writeback Level

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US Patent:
6580650, Jun 17, 2003
Filed:
Mar 16, 2001
Appl. No.:
09/810325
Inventors:
Wayne F. Ellis - Jericho VT
Russell J. Houghton - Essex Junction VT
Mark D. Jacunski - Colchester VT
Thomas M. Maffitt - Burlington VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 700
US Classification:
36518909, 365195
Abstract:
A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage V from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.

Wordline On And Off Voltage Compensation Circuit Based On The Array Device Threshold Voltage

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US Patent:
6693843, Feb 17, 2004
Filed:
Dec 13, 2002
Appl. No.:
10/318795
Inventors:
Thomas M. Maffitt - Burlington VT
Russell J. Houghton - Essex Junction VT
Mark David Jacunski - Colchester VT
William Robert Tonti - Essex Junction VT
Kevin McStay - Hopewell Junction NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800
US Classification:
36523006, 36518909, 365210, 365226
Abstract:
An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (âV â) monitor, a wordline on voltage (âV â) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (âV â) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

Precharging The Write Path Of An Mram Device For Fast Write Operation

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US Patent:
7057924, Jun 6, 2006
Filed:
Jan 15, 2004
Appl. No.:
10/758449
Inventors:
Stefan Lammers - South Burlington VT, US
Hans-Heinrich Viehmann - South Burlington VT, US
Thomas M. Maffitt - Burlington VT, US
John E. Barwin - Jeffersonville VT, US
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
G11C 11/14
US Classification:
365171, 365158, 365173
Abstract:
The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.

Apparatus And Method For Implementing Precise Sensing Of Pcram Devices

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US Patent:
7535783, May 19, 2009
Filed:
Oct 1, 2007
Appl. No.:
11/865134
Inventors:
John K. DeBrosse - Colchester VT, US
Thomas M. Maffitt - Burlington VT, US
Mark C. H. Lamorey - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/02
US Classification:
365208, 365207, 365209
Abstract:
A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
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Thomas M Maffitt from Burlington, VT, age ~67 Get Report