Search

Thomas P Kriz

from Okatie, SC
Age ~82

Thomas Kriz Phones & Addresses

  • Okatie, SC
  • Yorktown Heights, NY
  • Parksville, NY
  • 25 Barrack Hill Rd, Ridgefield, CT 06877 (203) 438-4860
  • Brant Lake, NY
  • Pleasant Valley, NY
  • Mount Pleasant, WI
  • New York, NY

Education

Degree: Associate degree or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Thomas P Kriz
Director, Vice President
THE AMERICAN TOBACCO COMPANY
Thomas Kriz
KRIZ CONSTRUCTION, INC
254 Keeler Dr, Ridgefield, CT 06877

Publications

Us Patents

Dma Asynchronous Mode Clock Stretch

View page
US Patent:
46112790, Sep 9, 1986
Filed:
Apr 14, 1983
Appl. No.:
6/485085
Inventors:
Mark E. Andresen - Norwalk CT
Thomas A. Kriz - Sandy Hook CT
Andrew S. Potemski - New Milford CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
G06F 100
US Classification:
364200
Abstract:
An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of data transfer (DTACK) timing. A late DTACK signal causes stretch of the clock controlled TXSTB transfer strobe to a length which will accommodate worst case memory access conditions of the asynchronous bus structure.

Data Processing System With Reorganization Of Disk Storage For Improved Paging

View page
US Patent:
46807039, Jul 14, 1987
Filed:
Jun 25, 1984
Appl. No.:
6/624485
Inventors:
Thomas A. Kriz - Sandy Hook CT
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
G06F 1212
G11B 2012
US Classification:
364200
Abstract:
In a data processor having a paging system, a list is kept of the disk seek time when a page of information is brought into processor memory from a disk storage device. (Seek time is the time for moving the disk read-write head radially inward or outward to the next track that is to be accessed. ) The average seek time for the pages in memory is calculated and is compared with a reference value of seek time. When the average reaches the reference, the pages in memory are reordered on the disk. This reordering takes place as the pages are bumped from memory in the normal process of paging, and the pages are relocated on the disk tracks in the physical order in which the pages were originally brought into memory. If approximately the same pages are fetched again in approximately the same sequence, the read-write head of the disk drive will be moved a shorter distance between successive disk accesses with reduced backtracking. The invention is particularly intended for a data processor of intermediate size that is large enough to use a paging system but small enough to use a disk drive that has an appreciable seek time.

Dma Multimode Transfer Controls

View page
US Patent:
45300534, Jul 16, 1985
Filed:
Apr 14, 1983
Appl. No.:
6/485084
Inventors:
Thomas A. Kriz - Sandy Hook CT
Andrew S. Potemski - New Milford CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 900
US Classification:
364200
Abstract:
Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microprocessor before transferring control of the data and address busses to the DMAC and generates one or both of two data transfer strobe signals which instruct the memory to transfer contiguous bytes, contiguous high alternate order bytes, or contiguous low alternate order bytes, or both.

Program Controlled Bus Arbitration For A Distributed Array Processing System

View page
US Patent:
49410865, Jul 10, 1990
Filed:
Feb 2, 1984
Appl. No.:
6/576303
Inventors:
Thomas A. Kriz - Sandy Hook CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13364
US Classification:
364200
Abstract:
A distributed array processing system includes a bus divided into two portions or segments by a switch. One segment is connected to a processor and to a bus arbiter for controlling use of the bus. The bus arbiter provides one source of bus grant signals. A control register provides a second source of bus grant signals and additional signals for disabling the arbiter and actuating the switch. The control register is software controlled, i. e. , it is loadable with data or control signals, under program control, to control use of the bus.

Isbn (Books And Publications)

Thermal Energy Storage for Process Heat and Building Applications

View page
Author

Thomas Kriz

ISBN #

0895531380

Thomas P Kriz from Okatie, SC, age ~82 Get Report