US Patent:
20020073295, Jun 13, 2002
Inventors:
Thomas Bowers - Warrenville IL, US
Robert Gamoke - Batavia IL, US
Glen Rocque - Aurora IL, US
Paul Wiley - Naperville IL, US
International Classification:
G06F012/02
US Classification:
711/200000, 711/214000, 711/220000
Abstract:
In a data processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses, having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data, an arrangement for extending a range of addressable storage beyond the basic range allowed by the instruction codes. The processor is equipped to generate a long address, i.e., 30-bits, even though the instruction execution means can only generate a 23-bit address. When the processor goes into an alternate mode, the contents of a segment control register are prefixed onto the addresses generated within the processor when a certain class of instructions are executed. In accordance with Applicants' preferred embodiment, the class of instructions which call for prefixing of the addresses generated when the processor is in the alternate mode, is an indication that the addresses being generated within the processor are base instruction range addresses for a data access, or base data access instructions for an instruction fetch. Advantageously, mode control can be accomplished within a single cycle. Advantageously, this arrangement allows for accessing memory and a segment control, and under base address control, without unduly limiting the range of the range of operations that can be performed from memory in the base range or the range controlled by the segment controller.