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Theodros Yigzaw

from Sherwood, OR
Age ~59
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Also known as:
Theo Yigzaw, Theodros Yigaw, F Yigzaw
Phone and address:
21505 Chapman Rd, Sherwood, OR 97140
(503) 625-4051
Related to:
Adane W Yigzaw, 51Rhoda Reck, 67Natasha Fullmer, 48Amber Reck, 71Jack Reck, 100Dennis Reck, 71
Connected to:
Tegegne Yigzaw, 71Chen Yih, 85Ching W Yih, 64Christopher J Yih, 36James S Yih, 38John T Yih, 64Sabrina Yih, 65Tsai H Yih, 89Cheung Yik, 55Chong Yik, 96

Theodros Yigzaw Phones & Addresses

  • 21505 Chapman Rd, Sherwood, OR 97140 (503) 625-4051
  • 3025 159Th Ave, Beaverton, OR 97006 (503) 690-4433
  • Hillsboro, OR
  • Lincoln City, OR

Work

Company: Intel corporation May 2016 Position: Server platform architect

Education

Degree: Bachelor of Science, Masters, Bachelors, Master of Engineering School / High School: Cornell University 1985 to 1990 Specialities: Engineering

Skills

Semiconductors • Processors • Asic • Verilog • Embedded Systems • Soc • Debugging • Microprocessors • Computer Architecture • Design of Experiments • Hardware Architecture • Research • Product Management • Ic • Vlsi • Simulations • Rtl Design • Application Specific Integrated Circuits • Management • Perl • Operations Management

Industries

Computer Hardware

Resumes

Resumes

Theodros Yigzaw Photo 1

Server Platform Architect

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Location:
2751 southwest Beach Ave, Lincoln City, OR 97367
Industry:
Computer Hardware
Work:
Intel Corporation
Server Platform Architect
Intel Corporation 1990 - 2001
Component Design Engineer
Intel Corporation 1990 - 2001
Server Cpu Architect
Education:
Cornell University 1985 - 1990
Bachelor of Science, Masters, Bachelors, Master of Engineering, Engineering
Skills:
Semiconductors
Processors
Asic
Verilog
Embedded Systems
Soc
Debugging
Microprocessors
Computer Architecture
Design of Experiments
Hardware Architecture
Research
Product Management
Ic
Vlsi
Simulations
Rtl Design
Application Specific Integrated Circuits
Management
Perl
Operations Management

Publications

Us Patents

Performance Prioritization In Multi-Threaded Processors

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US Patent:
8275942, Sep 25, 2012
Filed:
Dec 22, 2005
Appl. No.:
11/316560
Inventors:
Theodros Yigzaw - Sherwood OR, US
Mark Rowland - Beaverton OR, US
Ganapati Srinivasa - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 13/00
US Classification:
711128, 711 3, 711118, 711130, 711131, 711149, 711154
Abstract:
According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

Injecting A Data Error Into A Writeback Path To Memory

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US Patent:
8645797, Feb 4, 2014
Filed:
Dec 12, 2011
Appl. No.:
13/323405
Inventors:
Theodros Yigzaw - Sherwood OR, US
Yen-Cheng Liu - Portland OR, US
Mohan J. Kumar - Aloha OR, US
Jose A. Vargas - Rescue CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 29/00
US Classification:
714768, 714 41
Abstract:
In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

Mechanism For Advanced Server Machine Check Recovery And Associated System Software Enhancements

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US Patent:
20130007507, Jan 3, 2013
Filed:
Jul 1, 2011
Appl. No.:
13/175407
Inventors:
Ashok Raj - Portland OR, US
Narayan Ranganathan - Portland OR, US
Mohan J. Kumar - Aloha Oregon OR, US
Theodros Yigzaw - Sherwood OR, US
International Classification:
G06F 11/00
US Classification:
714 511, 714E11016
Abstract:
Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

Method And Apparatus For Injecting Errors Into Memory

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US Patent:
20130275810, Oct 17, 2013
Filed:
Sep 29, 2011
Appl. No.:
13/992506
Inventors:
Theodros Yigzaw - Sherwood OR, US
Kai Cheng - Portland OR, US
Mohan J. Kumar - Aloha OR, US
Jose A. Vargas - Rescue CA, US
Gopikrishna Jandhyala - Milpitas CA, US
International Classification:
G06F 11/263
US Classification:
714 32
Abstract:
Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Machine Check Summary Register

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US Patent:
20130339829, Dec 19, 2013
Filed:
Dec 29, 2011
Appl. No.:
13/995458
Inventors:
Jose A. Vargas - Rescue CA, US
Mohan J. Kumar - Aloha OR, US
James B. Crossland - Banks OR, US
Murugasamy K. Nachimuthu - Beaverton OR, US
Theodros Yigzaw - Sherwood OR, US
International Classification:
G06F 11/10
US Classification:
714807
Abstract:
In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

Embedded Controller And Memory To Store Memory Error Information

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US Patent:
20220350500, Nov 3, 2022
Filed:
Jun 30, 2022
Appl. No.:
17/855688
Inventors:
- Santa Clara CA, US
Theodros YIGZAW - Sherwood OR, US
Sarathy JAYAKUMAR - Portland OR, US
Anthony LUCK - San Jose CA, US
Deep K. BUCH - Folsom CA, US
Rajat AGARWAL - Portland OR, US
Kuljit S. BAINS - Olympia WA, US
John G. HOLM - Beaverton OR, US
Brent CHARTRAND - Folsom CA, US
Keith KLAYMAN - Folsom CA, US
International Classification:
G06F 3/06
Abstract:
An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.

Adaptive Ras Platform Based On Correlative Prediction

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US Patent:
20220334736, Oct 20, 2022
Filed:
Jul 1, 2022
Appl. No.:
17/856637
Inventors:
- Santa Clara CA, US
Karthik Kumar - Chandler AZ, US
Thomas Willhalm - Sandausen, DE
Hsing-Min Chen - Santa Clara CA, US
Theodros Yigzaw - Sherwood OR, US
Russell Clapp - Portland OR, US
Saravanan Sethuraman - Bayan Lepas, MY
Patricia Mwove Shaffer - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/06
Abstract:
An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

Device, System, And Method To Concurrently Store Multiple Pmon Counts In A Single Register

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US Patent:
20220196733, Jun 23, 2022
Filed:
Dec 22, 2020
Appl. No.:
17/131477
Inventors:
- Santa Clara CA, US
Subhankar Panda - Portland OR, US
Theodros Yigzaw - Sherwood OR, US
John Holm - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/317
Abstract:
Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.
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Theodros Yigzaw from Sherwood, OR, age ~59 Get Report