Search

Theodore C Lemmond

from Portland, OR
Age ~61
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Also known as:
Ted C Lemmond, Ted A Lemmond, Theodore C Trs, Theodore C Lemmonds, Theordore Lemmond
Phone and address:
3475 Banyon Pl, Portland, OR 97229
(503) 645-5637
Related to:
Charles Q LemmondLesley Eaves, 49Linda Critelli, 62Matthew Lemmond, 29Beverly Lemmond, 97
Connected to:
Caroline J Lemmond, 59Joyce D Lemmonds, 69Marcia J Lemmond, 69Mason T Lemmond, 46Patti B Lemmond, 64Vicki S Lemmond, 56Blake L Lemmons, 50Brent Lemmons, 39Colby Lemmons, 35Crystal Lemmons, 48

Theodore Lemmond Phones & Addresses

  • 3475 Banyon Pl, Portland, OR 97229 (503) 645-5637
  • Mossyrock, WA
  • 16605 Torrey Pines Ct, Beaverton, OR 97006
  • 2529 Rogue Valley Ter, Beaverton, OR 97006
  • Sunriver, OR

Work

Position: Medical Professional

Education

Degree: Graduate or professional degree

Interests

job inquiries, reference requests, getti...

Industries

Design

Resumes

Resumes

Theodore Lemmond Photo 1

Senior Engineer At Intel

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Location:
Portland, Oregon Area
Industry:
Design
Experience:
Intel (Public Company; 10,001 or more employees; INTC; Semiconductors industry): Senior Engineer,  (July 1987-Present) Senior Component Engineer supporting layout verification for the 30nm WMT microprocessor.

Publications

Us Patents

Process For Eliminating Effect Of Polysilicon Stringers In Semiconductor Devices

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US Patent:
56396813, Jun 17, 1997
Filed:
Jan 17, 1995
Appl. No.:
8/372992
Inventors:
Kevin F. Carmody - Portland OR
Theodore C. Lemmond - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 218247
US Classification:
437 52
Abstract:
A process for eliminating the effects of parasitic paths from stringers by forming diversionary paths in the overhangs in which the stringers are formed. The diversionary paths are selected such that the stringers formed in these paths are harmless to the operation of the circuit. For instance, in the formation of floating gate memory array where first and second polysilicon lines are formed are right angles to each other and then the first lines are etched in alignment with the second line to form the floating gates the invention is implemented by forming gaps in the first lines between the second lines. In this way, stringers formed from the second polysilicon layer are diverted. Consequently, the parasitic paths are paths in parallel with the second lines (word lines) instead of shorts between adjacent word lines.
Control profile
Theodore C Lemmond from Portland, OR, age ~61 Get Report