Inventors:
Feng Pan - San Jose CA
Tat-Kwan Edgar Yu - Cupertino CA
Assignee:
Sandisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
3651853, 36518529, 36518524
Abstract:
Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.