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Tahoma Madrone Toelkes

from Cupertino, CA
Age ~50
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Also known as:
Tahoma M Toelkes, Tahoma Madrona Toelkes, Thoma M Toelkes, Thaoma Toelkes, Tahoma M Toelles, Madrone Toelkes Tahoma, Toelkes Thoma, Felice Schimmel
Phone and address:
19500 Pruneridge Ave #3209, Cupertino, CA 95014
Related to:
Nella M Hunter, 51Scot Chandler, 51William Harbison, 69Richard Ritscher, 99Gerald Navarra, 60Mary J Navarra, 58
Connected to:
Dell Toelkes, 58Bruce E Toelle, 48Christopher A Toelle, 53Craig A Toelle, 55John P Toelle, 68Troy Toelle, 57Jayne M Toellner, 71Jonathan D Toellner, 35Kathleen Toellner, 71Richard R Toellner, 60

Tahoma Toelkes Phones & Addresses

  • 19500 Pruneridge Ave #3209, Cupertino, CA 95014
  • 1605 Wethersfield Rd, Austin, TX 78703
  • 1601 Kinney Ave #334, Austin, TX 78704
  • 1316 Keoncrest Ave, San Jose, CA 95110 (512) 826-7032
  • 535 S Market St #311, San Jose, CA 95113 (785) 837-3516
  • Lawrence, KS

Work

Position: Clerical/White Collar

Education

Degree: Associate degree or higher

Resumes

Resumes

Tahoma Toelkes Photo 1

Core Os - Prototype Bring Up - Ios Embedded Bring Up Engineer

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Location:
1605 Wethersfield Rd, Austin, TX 78703
Industry:
Computer Software
Work:
Apple
Core Os - Prototype Bring Up - Ios Embedded Bring Up Engineer
Apple Sep 2015 - Sep 2017
Coreos - New Product Architecture - Platform Generalist
Apple Jun 2012 - Sep 2015
Core Os - Platform Debug - Tools Lead
Apple Jun 2008 - Jun 2012
Core Os - Ios Platform Team - Kernel Engineer
Apple Mar 2007 - Jun 2008
Ipod - Firmware - Nand Engineer
Education:
The University of Kansas 1994 - 1999
Missouri State University 1992 - 1993
Skills:
Embedded Systems
Device Drivers
C
Perl
Firmware
Debugging
Software Development
Linux
Python
C++
Verilog
Embedded Software
Soc
Xml
Digital Signal Processors
Testing
Operating Systems
Linux Kernel
System Architecture
Objective C
Bash
Programming
Os X
Software Engineering
Kernel
Usb
Java
Hardware
Microprocessors
Rtos
Storage
Sql
Arm
Software Design
Unix
Shell Scripting
Databases
Simulations
Manufacturing
Distributed Systems
Vhdl
Algorithms
Scheme
Subversion
Embedded Linux
Solaris
Tcp/Ip
Assembly
Mac Os X
Application Development
Interests:
Human Rights
Science and Technology
Environment
Health
Languages:
Spanish
English
Tahoma Toelkes Photo 2

Tahoma Toelkes

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Publications

Us Patents

Method And Apparatus For Booting From A Flash Memory Without Prior Knowledge Of Flash Parameter Information

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US Patent:
8171277, May 1, 2012
Filed:
Jul 2, 2008
Appl. No.:
12/167112
Inventors:
Michael Smith - San Francisco CA, US
Nir Wakrat - San Jose CA, US
Tahoma Toelkes - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 15/177
US Classification:
713 2, 4555561, 711103
Abstract:
Techniques for booting a computing device with a flash memory without knowledge of parametric information of the flash memory are described herein. In one embodiment of the invention, the computing device receives input requesting the computing device to begin operation and executes a set of one or more instructions stored in a non-volatile memory. The execution of the set of instructions configures a first read routine for accessing the flash memory based on a common denominator format of candidate flash memories, and the first read routine is not configured based on information located in a flash memory identification table. The computing device reads a bootstrapping code image based on the first read routine into a volatile memory and executes that first bootstrapping code image. Other methods and apparatuses are also described.

Device Bootup From A Nand-Type Non-Volatile Memory

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US Patent:
8205070, Jun 19, 2012
Filed:
Sep 8, 2009
Appl. No.:
12/555306
Inventors:
Tahoma M. Toelkes - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 15/177
US Classification:
713 2, 713 1, 711103
Abstract:
Systems and methods are provided for using a NAND-type non-volatile memory (“NVM”), such as NAND flash memory, to store NV pre-boot information for a bootloader (e. g. , a second state bootloader) or an operating system. The NV pre-boot information can include, for example, environment variables storing the configuration or state of an electronic device. In some embodiments, an electronic device including the NAND-type NVM may allocate a portion of the super blocks in the NAND-type NVM to storing the NV pre-boot information. The electronic device may store a redundant copy of the NV pre-boot information into the allocated portion of each IC die of the NAND-type NVM.

Multipage Preparation Commands For Non-Volatile Memory Systems

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US Patent:
8321647, Nov 27, 2012
Filed:
Aug 20, 2009
Appl. No.:
12/545011
Inventors:
Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Los Altos CA, US
Tahoma Toelkes - San Jose CA, US
Daniel Jeffrey Post - Campbell CA, US
Anthony Fai - Palo Alto CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 13/00
G06F 13/28
US Classification:
711170, 711154, 711E12002
Abstract:
Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Command Queue For Peripheral Component

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US Patent:
8332543, Dec 11, 2012
Filed:
Jan 27, 2012
Appl. No.:
13/359533
Inventors:
Douglas C. Lee - Cupertino CA, US
Diarmuid P. Ross - Mountainview CA, US
Tahoma M. Toelkes - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 5, 710 8, 710 22, 710 30, 710 39
Abstract:
In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Architecture For Address Mapping Of Managed Non-Volatile Memory

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US Patent:
8370603, Feb 5, 2013
Filed:
Nov 6, 2009
Appl. No.:
12/614369
Inventors:
Tahoma Toelkes - San Jose CA, US
Nir Jacob Wakrat - Los Altos CA, US
Kenneth L. Herman - San Jose CA, US
Barry Corlett - Brisbane CA, US
Vadim Khmelnitsky - Foster City CA, US
Anthony Fai - Palo Alto CA, US
Daniel Jeffrey Post - Campbell CA, US
Hsiao Thio - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/34
G06F 9/26
US Classification:
711202, 711103
Abstract:
The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Command Queue For Peripheral Component

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US Patent:
8396994, Mar 12, 2013
Filed:
Nov 9, 2012
Appl. No.:
13/672989
Inventors:
Diarmuid P. Ross - Mountain View CA, US
Tahoma M. Toelkes - Mountain View CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 5, 710 15, 710 22, 710 30, 710 39
Abstract:
In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Dynamically Allocating Number Of Bits Per Cell For Memory Locations Of A Non-Volatile Memory

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US Patent:
8402243, Mar 19, 2013
Filed:
Feb 25, 2010
Appl. No.:
12/712540
Inventors:
Nir J. Wakrat - Los Altos CA, US
Tahoma M. Toelkes - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 12/00
G06F 12/02
US Classification:
711170, 711103, 711202, 711E12001, 711E12008
Abstract:
Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

System And Method For Wiping Encrypted Data On A Device Having File-Level Content Protection

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US Patent:
8433901, Apr 30, 2013
Filed:
Apr 7, 2010
Appl. No.:
12/756094
Inventors:
Dallas Blake De Atley - San Francisco CA, US
Gordon Freedman - Palo Alto CA, US
Tahoma Madrone Toelkes - San Jose CA, US
Michael John Smith - San Francisco CA, US
Paul William Chinn - San Jose CA, US
David Rahardja - Sunnyvale CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H04L 29/06
G06F 11/30
G06F 7/04
US Classification:
713165, 713166, 713193, 726 26
Abstract:
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for erasing user data stored in a file system. The method includes destroying all key bags containing encryption keys on a device having a file system encrypted on a per file and per class basis, erasing and rebuilding at least part of the file system associated with user data, and creating a new default key bag containing encryption keys. Also disclosed herein is a method of erasing user data stored in a remote file system encrypted on a per file and per class basis. The method includes transmitting obliteration instructions to a remote device, which cause the remote device to destroy all key bags containing encryption keys on the remote device, erase and rebuild at least part of the file system associated with user data, and create on the remote device a new default key bag containing encryption keys.
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Tahoma Madrone Toelkes from Cupertino, CA, age ~50 Get Report