Tae Hee Lee

6355563, Mar 12, 2002

Mar 5, 2001

09/798652

Randall Cher Liang Cha - Singapore, SG
Alex See - Singapore, SG
Yeow Kheng Lim - Singapore, SG
Tae Jong Lee - Orlando FL
Lap Chan - San Francisco CA

Chartered Semiconductor Manufacturing Ltd. - Singapore

H01L 2144

438687, 438624, 438625, 438626, 438627, 438629, 438631, 438633, 438637, 438638, 438666, 438669, 438672, 438675

A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

6387747, May 14, 2002

May 31, 2001

09/867561

Randall Cha - Singapore, SG
Tae Jong Lee - Orlando FL
Alex See - Singapore, SG
Lap Chan - San Francisco CA
Chua Chee Tee - Singapore, SG

Chartered Semiconductor Manufacturing Ltd. - Singapore

H01L 218244

438238, 438381, 438687

A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

6468880, Oct 22, 2002

Mar 15, 2001

09/805954

Yeow Kheng Lim - Singapore, SG
Randall Cher Liang Cha - Singapore, SG
Alex See - Singapore, SG
Tae Jong Lee - Orlando FL
Wang Ling Goh - Singapore, SG

Chartered Semiconductor Manufacturing Ltd. - Singapore

H01L 2130

438459, 438311, 438406, 438977, 257347

A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e. g. , STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions.

6613652, Sep 2, 2003

Mar 14, 2001

09/805707

Yeow Kheng Lim - Singapore, SG
Randall Cher Liang Cha - Singapore, SG
Alex See - Singapore, SG
Tae Jong Lee - Orlando FL
Wang Ling Goh - Singapore, SG

Chartered Semiconductor Manufacturing Ltd. - Singapore

H01L 2130

438459, 438311, 438406, 438455, 438456

A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e. g. , STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

63197677, Nov 20, 2001

Mar 5, 2001

9/798639

Randall Cher Liang Cha - Singapore, SG
Tae Jong Lee - Orlando FL
Alex See - Singapore, SG
Lap Chan - San Francisco CA
Yeow Kheng Lim - Singapore, SG

Chartered Semiconductor Manufacturing Ltd. - Singapore

H01L 218242
H01L 214763

438250

A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask.

20190090586, Mar 28, 2019

Sep 28, 2017

15/719536

Tae Lee - Agoura Hills CA, US

Severus Products, LLC - Agoura Hills CA

A43B 17/14

A shoe insole with an upper surface covered with numerous, small elastomer nodules with outstanding non-slip, gripping properties that grip and cushion the foot, to eliminate movement or slippage of the foot inside a shoe and thereby help wearers avoid foot or toe injury when playing sports.

20170334747, Nov 23, 2017

May 19, 2017

15/600560

- Oakland CA, US
Anditya Rahardianto - Los Angeles CA, US
Tae Kyung Lee - Van Nuys CA, US

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

C02F 1/44
B01D 61/58
B01D 61/02

A membrane process unit (MPU) is configured to receive a feed stream, subject the feed stream to membrane purification to generate a product stream and a concentrate stream, and subject the concentrate stream to energy recovery to provide at least a portion of energy for membrane purification. A concentrate recycle unit (CRU) is configured to receive the concentrate stream from the MPU, subject the concentrate stream to flow regulation to generate a waste stream and a recycled concentrate stream, and combine the recycled concentrate stream with a raw feed stream to generate the feed stream which is supplied to the MPU. At least one of a flow rate of the raw feed stream, a flow rate of the waste stream, or a flow rate of the recycled concentrate stream is varied, while each of a flow rate of the feed stream, a flow rate of the product stream, and a flow rate of the concentrate stream is maintained substantially fixed.