Resumes
Resumes
Swapna Kale
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Swapna Kale Los Angeles, CA
View pageWork:
IHS iSuppli
May 2011 to 2000
Semiconductor Research Analyst
Design
Sep 2010 to Nov 2010
DDR2 controller
Design
Sep 2010 to Nov 2010
Preprocessor, Logic Simulator, Fault Simulator, ATPG and Post-processor
Design
Mar 2010 to May 2010
16 Bit Multiplier
MOS VLSI Circuit Design
Sep 2009 to Sep 2009
5 Stage Pipelined Processor Design
May 2011 to 2000
Semiconductor Research Analyst
Design
Sep 2010 to Nov 2010
DDR2 controller
Design
Sep 2010 to Nov 2010
Preprocessor, Logic Simulator, Fault Simulator, ATPG and Post-processor
Design
Mar 2010 to May 2010
16 Bit Multiplier
MOS VLSI Circuit Design
Sep 2009 to Sep 2009
5 Stage Pipelined Processor Design
Education:
University Of Southern California
Jun 2009 to May 2011
Masters of Science in Electrical Engineering
Jun 2009 to May 2011
Masters of Science in Electrical Engineering
Swapna Kale Los Angeles, CA
View pageWork:
IHS Inc
Jan 2014 to 2000
Electronics and Telecom Analyst
IHS iSuppli
Los Angeles, CA
May 2011 to Jan 2014
Semiconductor Research Analyst
VLSI System Design
Sep 2010 to Nov 2010
DDR2 controller Design
Diagnosis & Design of Reliable Digital Systems
Sep 2010 to Nov 2010
Fault Simulator, ATPG and Post-processor Design
Solid State Processing and Integrated Circuits
Apr 2010 to Jun 2010
Solid State Fabrication and Analysis
VLSI System Design
Apr 2010 to Jun 2010
16 bit Multiplier Design
Computer System Organization/Architechture
Apr 2009 to Jun 2009
5 Stage Pipelined Processor Design
Jan 2014 to 2000
Electronics and Telecom Analyst
IHS iSuppli
Los Angeles, CA
May 2011 to Jan 2014
Semiconductor Research Analyst
VLSI System Design
Sep 2010 to Nov 2010
DDR2 controller Design
Diagnosis & Design of Reliable Digital Systems
Sep 2010 to Nov 2010
Fault Simulator, ATPG and Post-processor Design
Solid State Processing and Integrated Circuits
Apr 2010 to Jun 2010
Solid State Fabrication and Analysis
VLSI System Design
Apr 2010 to Jun 2010
16 bit Multiplier Design
Computer System Organization/Architechture
Apr 2009 to Jun 2009
5 Stage Pipelined Processor Design
Education:
University Of Southern California
Jun 2009 to May 2011
Master of Science in Electrical Engineering
Sardar Patel Institute of Technology
Mumbai, Maharashtra
2005 to 2009
BS in Electronics Engineering
Jun 2009 to May 2011
Master of Science in Electrical Engineering
Sardar Patel Institute of Technology
Mumbai, Maharashtra
2005 to 2009
BS in Electronics Engineering
Skills:
Hardware Description: VHDL, VERILOG RTL; Design and Simulation tools: Modelsim, Cadence Virtuoso, Electronic Product Design (ePD), HSPICE, LT SPICE; Computer Skills: C, C++, MATLAB, Windows, Mac OS X
Swapna Kale Los Angeles, CA
View pageWork:
X-Cog Technologies Pvt. Ltd., India
Los Angeles, CA
May 2010 to Aug 2010
Summer Intern
Los Angeles, CA
May 2010 to Aug 2010
Summer Intern
Education:
University Of Southern California
Los Angeles, CA
Jan 2009 to Jan 2011
Master's in Electrical Engineering
Los Angeles, CA
Jan 2009 to Jan 2011
Master's in Electrical Engineering
Skills:
Verilog, Assembly level programming 8085,8086, Windows,Unix/Linux, Cadence, Spice, Matlab, ePD, C, C++