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Swamy V Punyamurtula

from Austin, TX
Age ~56
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Also known as:
Swamy Savithri Punyamurtula, Swamy P Punyamurtula, Swamy V Punyamurthula, Swamy Punyamurtula Sierra, Savithri V Punyamurtula, Venka Punyamurtula Swamy, Venkata Punyamurtula Swamy, Puny Amurtula Swamy, Punyamurtula Swamy, A Swamy
Phone and address:
6005 Sierra Leon APT 1512, Austin, TX 78759
(512) 280-0865
Related to:
Jeya L Suresh, 50S Punyamurtula, 56Savithri Punyamurtula, 52Parthasarathy Thirumalai, 59Thirumalais VijiSuresh Thirumalaisw, 55Vijayas Thirumalaiswamy, 57
Connected to:
Srujana Punyapu, 41Jeffrey V Punyasavatsut, 47Janet I Punzak, 92Alizza T Punzalan, 48Anita Punzalan, 75Archie E Punzalan, 44Carmina R Punzalan, 40Darren L Punzalan, 47Edwin R Punzalan, 62Emmanuel F Punzalan, 65

Swamy Punyamurtula Phones & Addresses

  • 6005 Sierra Leon APT 1512, Austin, TX 78759 (512) 280-0865
    • s
  • 6005 Sierra Leon, Austin, TX 78759
  • 2901 Windcliff Way, Austin, TX 78748 (512) 280-0865
  • 5701 Mo Pac Cir, Austin, TX 78749 (512) 899-0837
  • 2425 Cromwell Cir #407, Austin, TX 78741 (512) 389-2458
  • Spicewood, TX
  • Detroit, MI
  • 12440 Almda Trace Cir Apt 1512, Austin, TX 78727 (512) 750-6629

Work

Company: Amd Jul 2017 Position: Senior director, server performance group

Education

Degree: Master of Science, Masters School / High School: Wayne State University 1992 to 1994 Specialities: Computer Engineering

Skills

System Architecture • Microarchitecture • Microprocessors • Processors • High Performance Computing • Performance Engineering • Project Management • Performance Analysis • Soc • Functional Verification • Computer Architecture • Competitive Analysis • Processor Micro Architecture • Performance Modeling • High Performance Processor Design and Ve... • Low Power Design • X86 • Debugging • Project Execution • People Management • Organizational Efficiency Building • Perl • Device Drivers • Performance Tuning • Asic • Verilog • Semiconductors • Vlsi • Embedded Systems

Interests

Social Services • Children • Economic Empowerment • Education • Environment • Poverty Alleviation • Science and Technology • Disaster and Humanitarian Relief • Arts and Culture • Health

Industries

Semiconductors

Resumes

Resumes

Swamy Punyamurtula Photo 1

Senior Director, Server Performance Group

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Amd
Senior Director, Server Performance Group
Amd
Director, Design Engineering
Amd Sep 2008 - May 2010
Senior Technical Manager, Design Engineering
Amd Aug 2005 - Sep 2008
Senior Member, Technical Staff
Amd Aug 1994 - Aug 2005
Various Technical Roles
Education:
Wayne State University 1992 - 1994
Master of Science, Masters, Computer Engineering Madras Institute of Technology 1989 - 1991
Z.p.h. School (Boys) Tanuku 1978 - 1983
Skills:
System Architecture
Microarchitecture
Microprocessors
Processors
High Performance Computing
Performance Engineering
Project Management
Performance Analysis
Soc
Functional Verification
Computer Architecture
Competitive Analysis
Processor Micro Architecture
Performance Modeling
High Performance Processor Design and Verification
Low Power Design
X86
Debugging
Project Execution
People Management
Organizational Efficiency Building
Perl
Device Drivers
Performance Tuning
Asic
Verilog
Semiconductors
Vlsi
Embedded Systems
Interests:
Social Services
Children
Economic Empowerment
Education
Environment
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Arts and Culture
Health

Publications

Us Patents

Parallel Instruction Processing And Operand Integrity Verification

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US Patent:
7730346, Jun 1, 2010
Filed:
Apr 30, 2007
Appl. No.:
11/742029
Inventors:
David E. Kroesche - Austin TX, US
Swamy Punyamurtula - Austin TX, US
International Classification:
G06F 11/00
US Classification:
714 6, 714764, 714766
Abstract:
A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.

Hybrid Prefetch Method And Apparatus

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US Patent:
8583894, Nov 12, 2013
Filed:
Sep 9, 2010
Appl. No.:
12/878513
Inventors:
Swamy Punyamurtula - Austin TX, US
Bharath Narasimha Swamy - Bangalore, IN
Assignee:
Advanced Micro Devices - Sunnyvale CA
International Classification:
G06F 12/08
US Classification:
711213, 711137, 711E12004, 711E12057
Abstract:
A hybrid prefetch method and apparatus is disclosed. A processor includes a hybrid prefetch unit configured to generate addresses for accessing data from a system memory. The hybrid prefetch unit includes a first prediction unit configured to generate a first memory address according to a first prefetch algorithm and a second prediction unit configured to generate a second memory address according to a second prefetch algorithm. The hybrid prefetcher further includes an arbitration unit configured to select one of the first and second memory addresses and further configured to provide the selected one of the first and second memory addresses during a prefetch operation.

Microprocessor Including A Configurable Translation Lookaside Buffer

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US Patent:
20060277390, Dec 7, 2006
Filed:
Jun 7, 2005
Appl. No.:
11/146863
Inventors:
Gerald Zuraski - Austin TX, US
Swamy Punyamurtula - Austin TX, US
International Classification:
G06F 12/00
US Classification:
711207000
Abstract:
A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.

Store Aware Prefetching For A Datastream

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US Patent:
20110066811, Mar 17, 2011
Filed:
Sep 11, 2009
Appl. No.:
12/558465
Inventors:
Benjamin T. Sander - Austin TX, US
Bharath Narasimha Swamy - Bangalore, IN
Swamy Punyamurtula - Austin TX, US
International Classification:
G06F 12/08
G06F 12/00
US Classification:
711137, 711E12001, 711E12057
Abstract:
A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.

Page Aware Prefetch Mechanism

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US Patent:
20120131305, May 24, 2012
Filed:
Nov 22, 2010
Appl. No.:
12/951567
Inventors:
Swamy Punyamurtula - Austin TX, US
International Classification:
G06F 12/10
US Classification:
711204, 711E12059
Abstract:
A processor includes a prefetch aware prefetch unit having a storage with a number of entries, and each entry corresponds to a different prefetch data stream. Each entry may be configured to store information corresponding to a page size of the prefetch data stream, along with, for example, an address corresponding to the prefetch data stream. For each entry, the prefetch unit may be configured to determine whether a prefetch of data in the data stream will cross a page boundary associated with the data stream based upon the page size information.
Control profile
Swamy V Punyamurtula from Austin, TX, age ~56 Get Report