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Surya Veeraraghavan

from Austin, TX
Age ~62
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Also known as:
Svrya Veeraraghavan, Surya Veeraraghava
Phone and address:
2700 Greenlee Dr, Austin, TX 78703
(512) 477-6874
Related to:
Daniel Hynek, 91Joanne Hynek, 87Adrienne MargieDaniel Hynek, 54
Connected to:
Nandhini Veeraraghavan, 55Nanditha Veeraraghavelu, 39Ram K Veeraragavan, 33Ramesh Veeraraghavan, 47Thiru M Veeraraghavan, 60Vijayaraghavan Veeraraghavan, 44Lakshmi Veerareddy, 45Akim A Veerasammy, 50Ravi K Veeraswamy, 54Seshadri N Veeravalli, 67

Surya Veeraraghavan Phones & Addresses

  • 2700 Greenlee Dr, Austin, TX 78703 (512) 477-6874

Work

Company: Freescale semiconductor Position: Distinguished member technical staff

Education

School / High School: Indian Institute of Technology, Bombay

Skills

Cmos • Semiconductors • Ic • Soc • Semiconductor Industry • Asic • Silicon • Mixed Signal • Analog • Physical Design • Eda • Integrated Circuit Design • Design of Experiments • Failure Analysis • Vlsi • R&D • Debugging • Thin Films • Microelectronics • Perl • Tcl • Rtl Design • Process Integration • Static Timing Analysis

Industries

Semiconductors

Resumes

Resumes

Surya Veeraraghavan Photo 1

Design Platform Architect

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor
Distinguished Member Technical Staff
Education:
Indian Institute of Technology, Bombay
Skills:
Cmos
Semiconductors
Ic
Soc
Semiconductor Industry
Asic
Silicon
Mixed Signal
Analog
Physical Design
Eda
Integrated Circuit Design
Design of Experiments
Failure Analysis
Vlsi
R&D
Debugging
Thin Films
Microelectronics
Perl
Tcl
Rtl Design
Process Integration
Static Timing Analysis

Publications

Us Patents

Method For Forming A Semiconductor-On-Insulator (Soi) Body-Contacted Device With A Portion Of Drain Region Removed

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US Patent:
7446001, Nov 4, 2008
Filed:
Feb 8, 2006
Appl. No.:
11/349875
Inventors:
Leo Mathew - Austin TX, US
Lixin Ge - Austin TX, US
Surya Veeraraghavan - Austin TX, US
Assignee:
Freescale Semiconductors, Inc. - Austin TX
International Classification:
H01L 21/336
H01L 29/06
US Classification:
438283, 257288, 257619, 257623, 257E29263, 257E29264
Abstract:
A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Method And Apparatus For Forming An Soi Body-Contacted Transistor

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US Patent:
20050127442, Jun 16, 2005
Filed:
Dec 12, 2003
Appl. No.:
10/734435
Inventors:
Surya Veeraraghavan - Austin TX, US
Yang Du - Austin TX, US
Glenn Workman - Austin TX, US
International Classification:
H01L027/01
US Classification:
257347000, 438479000
Abstract:
A method for forming a silicon-on-insulator transistor () includes forming an active region () overlying an insulating layer (), wherein a portion of the active region provides an intrinsic body region (). A body tie access region () is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode () is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion () of the body tie access region. The gate electrode is formed having a substantially constant gate length () along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes () are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion () is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

Systems And Methods For Reducing Power Consumption In Semiconductor Devices

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US Patent:
20150015306, Jan 15, 2015
Filed:
Jul 12, 2013
Appl. No.:
13/940644
Inventors:
Anis M. Jarrar - Austin TX, US
Mark D. Hall - Austin TX, US
David R. Tipple - Leander TX, US
Surya Veeraraghavan - Austin TX, US
International Classification:
H03K 19/094
G06F 17/50
US Classification:
326102, 716113
Abstract:
A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.
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Surya Veeraraghavan from Austin, TX, age ~62 Get Report