Search

Surena Neshvad Phones & Addresses

  • Portland, OR
  • Hillsboro, OR
  • Sunnyvale, CA
  • Santa Clara, CA
  • Gainesville, FL

Publications

Us Patents

Method And Apparatus For Improving High Availability In A Pci Express Link Through Predictive Failure Analysis

View page
US Patent:
20080005706, Jan 3, 2008
Filed:
Jun 30, 2006
Appl. No.:
11/479417
Inventors:
Debendra Das Sharma - Santa Clara CA, US
Surena Neshvad - Hillsboro OR, US
Guru Rajamani - Sunnyvale CA, US
Hanh Hoang - Sunnyvale CA, US
International Classification:
G06F 17/50
US Classification:
716 4
Abstract:
A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.
Surena Neshvad from Portland, OR, age ~48 Get Report